onsemi-FQP55N06

Part #onsemi-FQP55N06
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onsemi-FQP55N06
May 2001  
TM  
QFET  
FQP55N06  
60V N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for low voltage applications such as automotive, DC/  
DC converters, and high efficiency switching for power  
management in portable and battery operated products.  
•
•
•
•
•
•
•
55A, 60V, R  
= 0.020
Ω
@V =
 
10 V  
DS(on) GS  
Low gate charge ( typical 35 nC)  
Low Crss ( typical
 
85 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
175
°
C maximum junction temperature rating  
D
!
“
! ”  
“
“
G
!
 
G
D
TO-220  
FQP Series  
S
!
S
Absolute Maximum Ratings  
T =
 
25°C unless otherwise noted  
C
Symbol  
Parameter  
FQP55N06  
60  
Units  
V
V
I
Drain-Source Voltage  
DSS  
– Continuous (T
 
= 25°C)  
Drain Current  
55  
A
D
C
– Continuous (T
 
= 100°C)  
38.9  
220  
A
C
I
(Note 1)  
Drain Current  
– Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
±
25  
V
GSS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
545  
mJ  
A
AS  
55  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
13.3  
7.0  
mJ  
V/ns  
W
AR  
dv/dt  
P
Power Dissipation (T
 
= 25°C)  
133  
D
C
– Derate above 25°C  
Operating and Storage
T
e
mperature Range  
0.89  
-55 to +175  
W/°C  
°C  
T , T  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8
”
from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Case-to-Sink  
Thermal Resistance, Junction-to-Ambient  
Typ  
—  
Max  
1.13  
—  
Units  
°C
/
W  
°C
/
W  
°C
/
W  
R
R
R
θ
JC  
θ
CS  
θ
JA  
0.5  
—  
62.5  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Electrical Characteristics  
T =
 
25°C unless otherwise noted  
C
Symbol  
Parameter  
Test Conditions  
Min  
T
y
p  
Max  
Units  
Off Characteristics  
BV  
V
= 0
V
, I
 
=
2
50
µ
A  
GS D  
Drain-Source Breakdown Voltage  
60  
—  
—  
—  
—  
V
DSS  
∆
BV  
Breakdown Voltage
T
e
mperature  
Coefficient  
DSS  
J
I
= 250
µ
A, Referenced to 25°C  
0.06  
V/°C  
D
/
I
∆
T  
V
V
V
V
= 60
V
, V
 
= 0 V  
—  
—  
—  
—  
—  
—  
—  
—  
1
µ
A  
µ
A  
nA  
nA  
DSS  
DS  
GS  
Zero Gate Voltage Drain Current  
= 48
V
, T
 
=
1
50°C  
10  
DS  
GS  
GS  
C
I
I
= 25
V
, V
 
= 0 V  
Gate-Body Leakage Current, Forward  
Gate-Body Leakage Current, Reverse  
100  
-100  
GSSF  
DS  
= -25
V
, V
 
= 0 V  
GSSR  
DS  
On Characteristics  
V
V
V
V
= V
 
, I
 
= 250
µ
A  
Gate Threshold Voltage  
2.0  
—  
—  
4.0  
V
Ω
S
GS(th)  
DS  
GS  
DS  
GS  
D
R
Static Drain-Source  
On-Resistance  
DS(on)  
=
1
0
V
,
I =
2
7.
5
A  
0.015 0.020  
D
g
= 25
V
, I
 
=
2
7.5 A  
(Note 4)  
Forward Transconductance  
—  
30  
—  
FS  
D
Dynamic Characteristics  
C
C
C
Input Capacitance  
—  
—  
—  
1300  
490  
85  
1690  
640  
pF  
pF  
pF  
iss  
V
= 25
V
, V
 
= 0 V,  
GS  
DS  
Output Capacitance  
oss  
rss  
f = 1.0 MHz  
Reverse Transfer Capacitance  
110  
Switching Characteristics  
t
t
t
t
Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
T
o
tal Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
—  
—  
—  
—  
—  
—  
—  
15  
130  
60  
40  
270  
130  
160  
46  
ns  
ns  
d(on)  
V
= 30
V
, I
 
=
2
7.5 A,  
DD  
D
r
R
= 25
Ω  
G
ns  
d(off)  
f
(Note 4, 5)  
(Note 4, 5)  
75  
ns  
Q
Q
Q
35  
nC  
nC  
nC  
g
V
V
= 48
V
, I
 
=
5
5 A,  
DS  
D
9.5  
15.5  
—  
= 10 V  
gs  
gd  
GS  
—  
Drain-Source Diode Characteristics and Maximum Ratings  
I
Maximum Continuous Drain-Source Diode Forward Current  
—  
—  
—  
—  
—  
—  
—  
55  
220  
1.5  
—  
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current  
SM  
V
t
V
V
= 0
V
, I
 
=
5
5 A  
Drain-Source Diode Forward Voltage  
Reverse Recovery Time  
—  
V
SD  
GS  
S
= 0
V
, I
 
=
5
5 A,  
55  
80  
ns  
nC  
rr  
GS  
S
dI /
 
dt = 100 A/
µ
s  
Q
(Note 4)  
Reverse Recovery Charge  
—  
F
rr  
Notes:  
1. Repetitive Rating : Pulse width limited by maximum junction temperature  
2. L = 210
µ
H, I
 
= 55A, V
 
= 25V, R
 
= 25
Ω,
Starting  
T =
 
25°C  
AS  
DD  
G
J
3. I
 
≤
55A, di/dt
≤
300A/
µ
s, V  
≤
BV  
Starting T =
 
25°C  
4. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%  
SD  
DD  
DSS, J  
5. Essentially independent of operating temperature  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Typical Characteristics  
V
Top :  
15.0

G

V

S  

10.0 V  
8.0 V  
7.0 V  
6.0 V  
5.5 V  
5.0 V  
10

2  

10

1  

10

0  

10

2  

10

1  

10

0  

Botto
m
:
4
.
5
V  
℃
175  
℃
25  
※
Notes :  
※
Notes :  
μ
1. V
 
= 25V  
2. 250
 
s Pulse Test  

DS

μ  
℃
-55  
1. 250
 
s Pulse Test  
2. T

C

=
2
5  
℃
-1  
10  
10  
10

0  

10

1  

2
4
6
8
V

G
S

,
G
ate-Source Voltage [V]  
V

D
S

,
D
rain-Source Voltage [V]  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
50  
40  
30  
20  
10  
0
10

2  

10

1  

10

0  

V

GS

= 10V  
V

GS

= 20V  
※
Notes :  
℃
175  
℃
25  
1. V
 
= 0V  
2. 250
 
s Pulse Test  
※
℃

GS

μ  
Note : T = 25  
J
0
50  
100  
150  
200  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
I

D

, Drain Current [A]  
V ,
 
S
ource-Drain voltage [V]  
SD  
Figure 3. On-Resistance Variation
 
vs.  
Drain Current and Gate Voltage  
Figure 4. Body Diode Forward Voltage  
Variation vs. Source Current  
and Temperature  
4000  
12  
10  
8
C

i
s
s

=
C

g
s

+
C

g
d

(
C

d
s

=
s
horted)  
C

o
ss

=
C

d
s

+ C  
gd  
C

rss

= C  
gd  
V

DS

= 30V  
V

DS

= 48V  
3000  
2000  
1000  
0
C
※
Notes :  
oss  
1. V

G
S

= 0 V  
2. f
=
1
M
Hz  
C
6
iss  
4
C
rss  
2
※
No
t
e :
I

D

= 55A  
35  
0
0
5
10  
15  
20  
25  
30  
40  
-1  
10  
10

0  

10

1  

Q

G

, Total Gate Charge [nC]  
V

D
S

,
D
rain-Source Voltage [V]  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Typical Characteristics
 
(Continued)  
1.2  
1.1  
1.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
※
Notes :  
1. V

G
S

= 0 V  
0.9  
0.8  
※
Notes :  
μ
2. I

D

=
2
50  
A
1. V

G
S

= 10 V  
2. I

D

= 27.5 A  
-100  
-50  
0
50  
100  
150  
200  
-100  
-50  
0
50  
100  
150  
200  
T,
J
unction Temperature [

o

C
]  
T,
J
unction Temperature [

o

C
]  
J
J
Figure 7. Breakdown Voltage Variation  
vs. Temperature  
Figure 8. On-Resistance Variation  
vs. Temperature  
10

3  

60  
50  
40  
30  
20  
10  
0
Ope
r
a
tio
n
i
n
T
hi
s
A
rea  
is Li
m
i
ted by R

D
S(on)  

100
µ
s  
10

2  

10

1  

10

0  

1 ms  
10 ms  
DC  
※
Notes :  
1. T

C

=
2
5

o  

2. T

J

=
1
75

o  

3. Single Pulse  
C
C
10

-1  

10

0  

10

1  

10

2  

25  
50  
75  
100  
125  
150  
175  
℃
T

C

, Case Temperature [  
]
V

DS

, Drain-Source Voltage [V]  
Figure 9. Maximum Safe Operating Area  
Figure 10. Maximum Drain Current  
vs. Case Temperature  
1 0

0  

D = 0
.
5  
※
N o t e s  
:
0
.
2  
℃
/W M
 
a
x
.  
1 .
 
Z

θ

C

(
t )  
=
1
.
1 3  
J
2 .
 
D u t y
 
F
a c t o r ,
 
D = t

1

/t

2  

0
.
1  
3 .
 
T

J M  

–
T

C  

=
P

D M
 

* Z
 

θ

C

(
t )  
J
1 0

–
1  

0
.
0 5  
P

DM  

0
.
0 2  
t

1  

0
.
0 1  
t

2  

s
i
n g le
 
p u ls e  
1 0

–
2  

1 0

–
5  

1 0

–
4  

1 0

–
3  

1 0

–
2  

1 0

–
1  

1 0

0  

1 0

1  

t

1  

, S
 
q u a r e
 
W a
 
v e
 
P u
l
s e
 
D u r a tio n
 
[s e c ]  
Figure 11. Transient Thermal Response Curve  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Gate Charge Test Circuit & Waveform  
V

GS  

Same Type  
50K
ꢀ
 
as DUT  
Q

g  

12V  
200nF  
10V  
300nF  
V

DS  

V

GS  

Q

gs  

Q

gd  

DUT  
3mA  
Charge  
Resistive Switching Test Circuit & Waveforms  
R

L  

V

DS  

90%  
V

DS  

V

DD  

V

GS  

R

G  

10%  
V

GS  

DUT  
10V  
t

d(on)  

t

r  

t

d(off)  

t

f  

t

on  

t

off  

Unclamped Inductive Switching Test Circuit & Waveforms  
BV

DSS  

——————–  
BV

DSS

– V

DD  

L
1
2
2
—-  
E

AS  

=
L I

AS  

V

DS  

I

D  

BV

DSS  

I

AS  

R

G  

V

DD  

I

D

(t)  
V

DD  

V

DS

(t)  
DUT  
10V  
t

p  

t

p  

Time  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
DUT  
V

DS  

_
I

SD  

L
Driver  
R

G  

Same Type  
as DUT  
V

DD  

V

GS  

• dv/dt controlled by
 
R

G  

• I

SD

controlled by pulse period  
Gate Pulse Width  
————————–  
V

GS  

D =  
Gate Pulse Period  
10V  
( Driver )  
I

FM

, Body Diode Forward Current  
I

SD  

di/dt  
( DUT )  
I

RM  

Body Diode Reverse Current  
Body Diode Recovery dv/dt  
V

SD  

V

DS  

( DUT )  
V

DD  

Body Diode  
Forward Voltage Drop  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

Package Dimensions  
TO-220  
4.50
±
0.20  
9.90
±
0.20  
(8.70)  
+0.10  
–0.05  
1.30  
ø3.60
±
0.10  
1.27
±
0.10  
1.52
±
0.10  
0.80
±
0.10  
+0.10  
–0.05  
0.50  
2.40
±
0.20  
2.54TYP  
2.54TYP  
[2.54
±
0.20
]  
[2.54
±
0.20
]  
10.00
±
0.20  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
SuperSOT™-3  
ACEx™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
DenseTrench™  
DOME™  
EcoSPARK™  
E

2

CMOS™  
EnSigna™  
FAST

®  

FASTr™  
FRFET™  
GlobalOptoisolator™  
GTO™  
OPTOPLANAR™  
PACMAN
™  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
TinyLogic™  
UHC™  
POP™  
PowerTrench

®  

QFET™  
HiSeC™  
QS™  
UltraFET

®  

VCX™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MICROWIRE™  
OPTOLOGIC™  
QT Optoelectronics™  
Quiet Series™  
SLIENT SWITCHER

®  

SMART START™  
Stealth™  
FACT™  
FACT Quiet Series™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
©2001 Fairchild Semiconductor Corporation  
Rev. H2