onsemi-FQPF2NA90
| Part # | onsemi-FQPF2NA90 |
Download  | onsemi-FQPF2NA90 |
September 2000
TM
QFET
FQPF2NA90
900V N-Channel
MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
•
•
•
•
•
•
1.7A, 900V, R
DS(on)
= 5.8
Ω
@ V
GS
= 10 V
Low gate charge ( typical 15 nC)
Low Crss ( typical
6.5 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
!
“
! ”
“
!
G
“
G D
S
TO-220F
FQPF Series
!
S
Absolute Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
V
DSS
Parameter
FQPF2NA90
Units
V
Drain-Source Voltage
900
1.7
I
D
– Continuous (T
C
= 25°C)
– Continuous (T
C
= 100°C)
– Pulsed
Drain Current
A
1.07
6.8
A
I
DM
(Note 1)
Drain Current
A
V
GSS
E
AS
I
AR
Gate-Source Voltage
±
30
310
V
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
1.7
E
AR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25°C)
3.9
mJ
V/ns
W
dv/dt
P
D
4.0
39
– Derate above 25°C
Operating and Storage
T
e
mperature Range
0.31
-55 to +150
W/°C
°C
T
J
, T
STG
T
L
Maximum lead temperature for soldering purposes,
300
°C
1/8
”
from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
—
Max
3.2
Units
°C
/
W
°C
/
W
R
θ
JC
R
θ
JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
—
62.5
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Electrical Characteristics
T =
25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
V
GS
= 0 V, I
D
= 250
µ
A
D
= 250
µ
A, Referenced to 25°C
Drain-Source Breakdown Voltage
900
—
—
—
—
V
∆
BV
DSS
Breakdown Voltage
T
e
mperature
I
1.0
V/°C
/
∆
T
J
Coefficient
I
DSS
V
DS
= 900
V
,
V
GS
= 0 V
DS
= 720
V
,
T
C
= 125°C
—
—
—
—
—
—
—
—
10
µ
A
µ
A
nA
nA
Zero Gate Voltage Drain Current
V
100
100
-100
I
GSSF
I
GSSR
V
GS
= 30
V
,
V
DS
= 0 V
V
GS
= -30 V, V
DS
= 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
On Characteristics
V
GS(th)
V
DS
= V
GS
, I
D
= 250
µ
A
Gate Threshold Voltage
3.0
—
—
5.0
5.8
—
V
Ω
S
R
DS(on)
Static Drain-Source
On-Resistance
V
G
S
=
1
0
V
,
I
D
=
0
.8
5
A
4.5
2.3
g
FS
V
DS
= 50
V
,
I
D
= 0.85 A
(Note 4)
Forward Transconductance
—
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
—
—
—
525
52
680
68
pF
pF
pF
V
DS
= 25
V
,
V
GS
= 0 V,
Output Capacitance
f = 1.0 MHz
Reverse Transfer Capacitance
6.5
8.5
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
—
—
—
—
—
—
—
17
40
30
30
15
3.7
7.5
45
90
70
70
20
—
ns
ns
V
DD
= 450
V
,
I
D
= 2.8 A,
R
G
= 25
Ω
ns
(Note 4, 5)
(Note 4, 5)
ns
Q
g
nC
nC
nC
V
DS
= 720
V
,
I
D
= 2.8 A,
Q
gs
Q
gd
V
GS
= 10 V
—
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
—
—
—
—
—
—
—
1.7
6.8
1.4
—
A
A
I
SM
V
SD
t
rr
Maximum Pulsed Drain-Source Diode Forward Current
V
GS
= 0 V, I
S
= 1.7 A
GS
= 0 V, I
S
= 2.8 A,
dI
F
/ dt = 100 A/
µ
s
Drain-Source Diode Forward Voltage
Reverse Recovery Time
—
V
V
500
2.6
ns
µ
C
(Note 4)
Q
rr
Reverse Recovery Charge
—
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 203mH, I
= 1.7A, V
= 50V, R
= 25
Ω,
Starting T =
25°C
AS
DD
G
J
3. I
≤
2.8A, di/dt
≤
200A/
µ
s, V
≤
BV Starting
T =
25°C
SD
DD
DSS, J
4. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Typical Characteristics
V
G
S
Top :
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
10
0
150
o
C
25
o
C
Bottom :
5.5 V
10
0
-1
10
-55
o
C
※
Notes :
μ
※
Notes :
1. 250
s Pulse Test
1. V
DS
= 50V
℃
2. T
C
= 25
μ
2. 250
s Pulse Test
-2
-1
10
10
-1
10
0
10
1
2
4
6
8
10
10
V
G
S
,
G
ate-Source Voltage [V]
V
D
S
,
D
rain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
10
9
8
7
6
5
4
3
2
V
G
S
= 10V
V
G
S
= 20V
10
0
℃
150
25
℃
※
Notes :
1. V
G
S
= 0V
※
℃
Note : T = 25
μ
2. 250
s Pulse Test
J
-1
10
0
1
2
3
4
5
6
0.2
0.4
0.6
0.8
1.0
1.2
I
D
,
D
rain Current [A]
V
SD
,
S
ource-Drain voltage [V]
Figure 3. On-Resistance Variation
vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
900
800
700
600
500
400
300
200
100
0
12
10
8
C
C
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
oss
= C
ds
+ C
gd
rss
= C
gd
V
D
S
= 180V
V
D
S
= 450V
C
iss
V
D
S
= 720V
C
oss
6
※
Notes :
1. V
G
S
= 0 V
2. f = 1 MHz
4
C
rss
2
※
Note : I
D
= 2.8 A
0
10
10
0
10
1
-1
0
4
8
12
16
Q
G
, Total Gate Charge [nC]
V
D
S
,
D
rain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate
Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Typical Characteristics
(Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※
Notes :
0.9
0.8
1. V
G
S
= 0 V
※
N
otes :
1. V
G
S
= 10 V
2. I
D
= 1.4 A
μ
A
2. I
D
=
2
50
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
o
C
]
T,
J
unction Temperature [
o
C
]
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.8
1.5
1.2
0.9
0.6
0.3
0.0
Operation in This Area
is Limited by R
D
S(on)
10
1
100
µ
s
1
m
s
10 ms
100 ms
10
0
DC
-1
10
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
3. Single Pulse
C
C
-2
10
10
0
10
1
10
2
10
3
25
50
75
100
125
150
℃
T
C
,
C
ase Temperature [
]
V
D
S
,
D
rain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case
Temperature
D = 0
.
5
1 0
0
0
.
2
※
N o
t
e s
1 .
Z
θ
J
C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
℃
/W M
a x.
=
3
.
2
0
.
1
3 .
T
J M
–
T
C
=
P
D
* Z
θ
J
C
(
t)
M
0
.
0 5
1 0
–
1
0
.
0 2
P
DM
0
.
0 1
t
1
t
2
s in g le
p u ls e
1 0
–
2
1 0
–
5
1 0
–
4
1 0
–
3
1 0
–
2
1 0
–
1
1 0
0
1 0
1
t
1
, S
q u a
r
e
W a
v e
P u ls e
D u ra tio n
[s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Gate Charge Test Circuit & Waveform
V
GS
Same Type
50K
Ω
as DUT
Q
g
12V
200nF
10V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
10V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
DSS
——————–
BV
DSS
– V
DD
L
1
2
2
—-
E
AS
=
L I
AS
V
DS
I
D
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
DD
V
DS
(t)
DUT
10V
t
p
t
p
Time
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Package Dimensions
TO-220F
2.54
±
0.20
10.16
±
0.20
ø3.18
±
0.10
(7.00)
(0.70)
(1.00×45
°
)
MAX1.47
0.80
±
0.10
#1
0.35
±
0.10
+0.10
–0.05
0.50
2.76
±
0.20
2.54TYP
2.54TYP
[2.54
±
0.20
]
[2.54
±
0.20
]
9.40
±
0.20
©2000 Fairchild Semiconductor International
Rev. A, September 2000
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2
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®
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PowerTrench
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
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which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1
