onsemi-FQPF5N60
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TM
QFET
FQPF5N60
600V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
•
•
•
•
•
•
•
2.8A, 600V, R
= 2.0
Ω
@V =
10 V
DS(on) GS
Low gate charge ( typical 16 nC)
Low Crss ( typical
9.0 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
TO-220F package isolation = 4.0kV
(Note 6)
D
!
“
! ”
“
G
!
“
TO-220F
G D S
!
S
FQPF Series
Absolute Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
Parameter
FQPF5N60
600
Units
V
V
I
Drain-Source Voltage
DSS
– Continuous (T
= 25°C)
Drain Current
2.8
A
D
C
– Continuous (T
= 100°C)
1.77
A
C
I
(Note 1)
Drain Current
– Pulsed
11.2
A
DM
V
E
I
Gate-Source Voltage
±
30
V
GSS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
300
mJ
A
AS
2.8
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
4.0
mJ
V/ns
W
AR
dv/dt
4.5
P
Power Dissipation (T
= 25°C)
40
D
C
– Derate above 25°C
Operating and Storage
T
e
mperature Range
0.32
W/°C
°C
T , T
-55 to +150
J
STG
Maximum lead temperature for soldering purposes,
T
300
°C
L
1/8
”
from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
Typ
—
Max
3.13
62.5
Units
°C
/
W
°C
/
W
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
θ
JC
θ
JA
—
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Electrical Characteristics
T =
25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
T
y
p
Max
Units
Off Characteristics
BV
V
= 0
V
, I
=
2
50
µ
A
GS D
Drain-Source Breakdown Voltage
600
—
—
—
—
V
DSS
∆
BV
Breakdown Voltage
T
e
mperature
Coefficient
DSS
J
I
= 250
µ
A, Referenced to 25°C
0.6
V/°C
D
/
I
∆
T
V
V
V
V
= 600
V
, V
= 0 V
—
—
—
—
—
—
—
—
10
100
100
-100
µ
A
µ
A
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 480
V
, T
=
1
25°C
DS
GS
GS
C
I
I
= 30
V
, V
= 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
GSSF
DS
= -30
V
, V
= 0 V
GSSR
DS
On Characteristics
V
V
V
V
= V
, I
= 250
µ
A
Gate Threshold Voltage
3.0
—
—
5.0
2.0
—
V
Ω
S
GS(th)
DS
GS
DS
GS
D
R
Static Drain-Source
On-Resistance
DS(on)
= 10
V
, I
= 1.4 A
1.57
3.5
D
g
= 50
V
, I
=
1
.4 A
(Note 4)
Forward Transconductance
—
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
—
—
—
560
80
9
730
100
12
pF
pF
pF
iss
V
= 25
V
, V
= 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
—
—
—
—
—
—
—
13
45
35
40
16
3.5
7.8
35
100
80
90
20
—
ns
ns
d(on)
V
= 300
V
, I
=
5
.0 A,
DD
D
r
R
= 25
Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
ns
Q
Q
Q
nC
nC
nC
g
V
V
= 480
V
, I
=
5
.0 A,
DS
D
= 10 V
gs
gd
GS
—
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
—
—
—
—
—
—
—
2.8
11.2
1.4
—
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0
V
, I
=
2
.8 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
—
V
SD
GS
S
= 0
V
, I
=
5
.0 A,
270
1.9
ns
µ
C
rr
GS
S
dI /
dt = 100 A/
µ
s
Q
(Note 4)
Reverse Recovery Charge
—
F
rr
Notes:
1. Repetitive
Rating : Pulse width limited by maximum junction temperature
2. L
= 70mH, I
= 2.8A, V
= 50V, R
= 25
Ω,
Starting T =
25°C
AS
DD
G
J
3.
I
≤
5.0A, di/dt
≤
200A/
µ
s, V
≤
BV Starting
T =
25°C
SD
DD
DSS, J
4. Pulse
Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
5. Essentially
independent of operating temperature
6. Only
for back side in V
= 4.0kV and t = 0.3s
iso
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Typical Characteristics
1
10
10
1
V
Top :
15
G
V
S
10 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom :
5.5 V
150
℃
25
℃
0
10
10
0
-55
℃
※
Notes :
※
Notes :
μ
-1
10
1. V
= 50V
DS
μ
1. 250
s Pulse Test
2. T
C
=
2
5
2. 250
s Pulse Test
℃
-1
10
-1
10
0
10
1
10
2
4
6
8
10
V
G
S
,
G
ate-Source Voltage
[V]
V
D
S
,
D
rain-Source Voltage
[V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
5
4
3
2
1
0
1
10
V
G
S
= 10V
V
G
S
= 20V
0
10
25
℃
150
℃
※
Notes :
1. V
= 0V
GS
μ
2. 250
s Pulse Test
※
℃
Note : T = 25
J
-1
10
0
2
4
6
8
10
12
14
0.2
0.4
0.6
0.8
1.0
1.2
1.4
I
D
, Drain Current [A]
V
S
D
,
S
ource-Drain Voltage
[V]
Figure 3. On-Resistance Variation
vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
1200
1000
800
600
400
200
0
12
C
iss
=
C
g
s
+
C
g
d
(C
d
s
= shorted)
C
o
ss
=
C
d
s
+ C
gd
C
rss
= C
V
DS
= 120V
V
DS
= 300V
V
DS
= 480V
gd
10
8
C
iss
C
oss
6
4
※
N
otes :
1. V
G
S
= 0 V
2. f = 1 MHz
C
rss
2
※
Note : I
D
= 5.0 A
15
0
0
3
6
9
12
18
-1
0
10
1
10
10
Q
G
, Total Gate Charge [nC]
V
D
S
,
D
rain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Typical Characteristics
(Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※
Note
s
:
1. V
= 0 V
0.9
0.8
2. I
D
G
=
S
2
50
A
※
Notes :
1. V
= 10 V
μ
2. I
D
G
=
S
2.5 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T,
J
unction Temperature [
o
C
]
T,
J
unction Temperature [
o
C
]
J
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
3.0
Operation in This Area
is Limited by R
DS(on)
2.5
2.0
1.5
1.0
0.5
0.0
10
1
100
µ
s
1
m
s
10 ms
100 ms
10
0
DC
-1
10
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
3. Single Pulse
C
C
-2
10
10
0
10
1
10
2
10
3
25
50
75
100
125
150
℃
T
C
, Case Temperature [
]
V
DS
,
D
rain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case
Temperature
D = 0
.
5
1 0
0
0
.
2
※
N o
t
e s
1 .
Z
θ
J
C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
℃
/W M
a x.
=
3
.
1 3
0
.
1
3 .
T
J M
–
T
C
=
P
D
* Z
θ
J
C
(
t)
M
0
.
0 5
1 0
–
1
0
.
0 2
P
DM
0
.
0 1
t
1
t
2
s
i
n g le
p u ls e
1 0
–
2
1 0
–
5
1 0
–
4
1 0
–
3
1 0
–
2
1 0
–
1
1 0
0
1 0
1
t
1
, S
q u a
r
e
W a
v e
P u ls e
D u ra tio n
[s e c ]
Figure 11. Transient Thermal Response Curve
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Gate Charge Test Circuit & Waveform
V
GS
Same Type
50K
ꢀ
as DUT
Q
g
12V
200nF
10V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
10V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
DSS
——————–
BV
DSS
– V
DD
L
1
2
2
—-
E
AS
=
L I
AS
V
DS
I
D
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
DD
V
DS
(t)
DUT
10V
t
p
t
p
Time
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
Package Dimensions
TO-220F
2.54
±
0.20
10.16
±
0.20
ø3.18
±
0.10
(7.00)
(0.70)
(1.00×45
°
)
MAX1.47
0.80
±
0.10
#1
0.35
±
0.10
+0.10
–0.05
0.50
2.76
±
0.20
2.54TYP
2.54TYP
[2.54
±
0.20
]
[2.54
±
0.20
]
9.40
±
0.20
Dimensions in Millimeters
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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FASTr™
FRFET™
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GTO™
ACEx™
Bottomless™
CoolFET™
CROSSVOL
T
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DOME™
EcoSPARK™
E
2
CMOS
TM
EnSigna
TM
FACT™
FACT Quiet Series™
FAST
â
POP™
HiSeC™
Power247™
PowerTrench
â
QFET™
I
2
C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
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QT Optoelectronics™
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T
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â
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â
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILIT
Y
A
RISING OUT OF THE APPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICE
S
O
R
S
YSTEM
S
W
ITHOU
T
T
H
E
E
XPRES
S
W
RITTE
N
A
PPROVA
L
O
F
F
AIRCHIL
D
S
EMICONDUCTO
R
C
ORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H7
