onsemi-FQS4900TF
| Part # | onsemi-FQS4900TF |
Download  | onsemi-FQS4900TF |
August 2000
TM
QFET
FQS4900
Dual N & P-Channel, Logic Level
MOSFET
General Description
Features
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
•
N-Channel 1.3A, 60V, R
R
P-Channel -0.3A, -300V, R
R
Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
Fast switching
= 0.55
Ω
@ V
= 10 V
GS
DS(on)
DS(on)
= 0.65
Ω
@ V
= 5 V
GS
= 15.5
Ω
@ V
= -10 V
DS(on)
GS
= 16
Ω
@ V
=- 5 V
DS(on)
GS
•
•
•
Improved dv/dt capability
!
5
6
7
8
4
3
2
1
!
“
!
!
!
D2
D2
D1
D1
G2
S2
G1
!
!
S1
#
$
!
!
Absolute Maximum Ratings
T
= 25°C unless otherwise noted
A
Symbol
Parameter
N-Channel
P-Channel
-300
Units
V
V
I
Drain-Source Voltage
60
1.3
DSS
– Continuous (T
= 25°C)
Drai
n
C
urrent
-0.3
A
D
A
– Continuous (T
= 70°C)
0.82
5.2
-0.19
A
A
I
(Note 1)
(Note 2)
Drai
n
C
urent
– Pulsed
-1.2
A
DM
V
Gate-Source Voltage
±
20
V
GSS
dv/dt
Peak Diode Recovery dv/dt
7.0
4.5
V/ns
W
P
Power Dissipation
(T =
25°C)
2.0
1.3
D
A
(T =
70°C)
W
A
T , T
Operating and Storage
T
e
mperature Range
-55 to +150
°C
J
STG
Thermal Characteristics
Symbol
Parameter
Typ
Max
Units
R
Thermal Resistance, Junction-to-Ambient
—
62.5
°C
/
W
θ
JA
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Electrical Characteristics
T =
25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Type
Min
T
y
p
Max
Units
Off Characteristics
V
V
V
V
V
V
V
V
= 0 V, I
=
2
50
µ
A
N-Ch
60
—
—
—
—
—
—
—
—
—
—
V
BV
Drain-Source Breakdown Voltage
GS
GS
DS
DS
DS
DS
GS
GS
D
DSS
= 0 V, I
=
–
250
µ
A
P-Ch -300
V
D
= 60 V, V
= 0 V
—
1
µ
A
µ
A
µ
A
µ
A
nA
nA
GS
I
Zero Gate Voltage Drain Current
DSS
N-Ch
—
= 48 V, T
= 55°C
10
-1
C
= -300 V, V
= 0 V
—
GS
P-Ch
—
= -240 V, T
= 55°C
-10
100
-100
C
I
I
= 20 V, V
= 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
All
All
—
—
GSSF
DS
= -20 V, V
= 0 V
GSSR
DS
On Characteristics
V
V
V
V
V
= 4
V
, I
=
2
0 mA
N-Ch
P-Ch
1.0
-1.0
—
—
1.95
-1.95
0.55
0.65
15.5
V
V
V
Gate Threshold Voltage
DS
DS
GS
GS
GS
D
GS(th)
= 4
V
, I
=
–
20 mA
—
D
R
= 10 V, I
= 0.65 A
Static Drain-Source On-Resistance
0.39
0.46
11.2
Ω
Ω
Ω
DS(on)
D
N-Ch
P-CH
= 5 V, I
=
0
.65 A
—
D
= -10 V, I
= -0.15 A
—
D
V
= -5 V, I
= -0.15 A
—
11.4
16
Ω
GS
D
V
V
= 10
V
, I
=
0
.65 A
N-CH
P-CH
—
—
1.7
0.6
—
—
S
S
g
Forward Transconductance
DS
DS
D
FS
= -10
V
, I
=
–
0.15 A
D
Switching Characteristics
t
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.7
10
21
30
50
60
32
80
45
105
2.1
4.7
—
ns
ns
ns
ns
ns
ns
ns
ns
nC
nC
nC
nC
nC
nC
N-Channel
d(on)
Turn-On Delay Time
V
= 30
V
, I
=
1
.3 A,
DD
D
t
21
R
= 25
Ω
r
G
Turn-On Rise Time
25
P-Channel
= -150 V, I
= -0.3 A,
t
t
11
d(off)
f
Turn-Off Delay Time
V
35
DD
D
R
= 25
Ω
17
G
Turn-Off Fall Time
T
o
tal Gate Charge
47
Q
Q
Q
1.6
3.6
0.28
0.42
0.82
2.1
N-Channel
g
V
= 48 V, I
= 1.3 A,
DS
D
V
= 5 V
Gate-Source Charge
Gate-Drain Charge
GS
gs
gd
P-Channel
—
V
= -240 V, I
= -0.3 A,
D
—
DS
GS
V
= -5 V
—
Drain-Source Diode Characteristics and Maximum Ratings
I
N-Ch
P-Ch
N-Ch
—
—
—
—
—
—
1.3
-0.3
1.5
A
A
V
Maximum Continuous Drain-Source Diode Forward Current
S
V
V
= 0 V, I
=
1
.3 A
V
Drain-Source Diode Forward Voltage
GS
GS
S
SD
= 0 V, I
= -0.3 A
P-Ch
—
—
-4.0
V
S
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
3. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
4. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Typical Characteristics : N-Channel
V
GS
Top :
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
10
0
B
ottom :
3.0 V
10
0
℃
150
℃
25
℃
-55
※
※
Notes :
Notes :
μ
1. 250
s Pulse Test
1. V
D
S
= 25V
℃
2. T
C
= 25
μ
2. 250
s Pulse Test
-1
10
-1
10
-1
10
10
0
10
1
0
2
4
6
8
10
V
GS
, Gate-Source Voltage [V]
V
DS
,
D
rain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
2.0
1.5
1.0
0.5
0.0
V
GS
= 10V
10
0
V
GS
= 5V
℃
℃
25
150
※
Notes :
1. V
GS
= 0V
※
℃
Note : T
= 25
μ
2. 250
s Pulse Test
J
-1
10
0
2
4
6
8
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
I
D
, Drain Current [A]
V
SD
, Source-Drain voltage [V]
Figure 3. On-Resistance Variation
vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
C
iss
= C
g
s
+ C
g
d
(C
d
s
= shorted)
oss
= C
d
s
+ C
g
d
C
rss
= C
g
d
C
160
120
80
※
Notes :
V
DS
= 30V
V
DS
= 48V
1. V
G
S
= 0 V
2. f = 1 MHz
C
iss
C
oss
6
4
40
C
rss
2
※
Note : I
D
= 1.3 A
2.5
0
0
0.0
10
-1
10
0
10
1
0.5
1.0
1.5
2.0
3.0
Q
G
, Total Gate Charge [nC]
V
DS
, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate
Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Typical Characteristics : N-Channel
(Continued)
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※
N
otes :
1. V
G
S
= 0 V
2. I
D
=
2
50
μ
A
0.9
※
Notes :
1. V
G
S
= 10 V
2. I
D
= 0.65 A
0.8
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
o
C
]
T
J
, Junction Temperature [
o
C
]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.5
1.2
0.9
0.6
0.3
0.0
Operation in This Area
is Limited by R
DS(on)
10
1
10
0
1 ms
10 ms
100 ms
1 s
10 s
DC
-1
10
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
3. Single Pulse
C
C
-2
10
10
10
0
10
1
10
2
-1
25
50
75
100
125
150
℃
T
C
, Case Temperature [
]
V
DS
, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case
Temperature
D = 0
.
5
0
.
2
1 0
1
※
N o
t
e s
1 .
Z
θ
J C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
0
.
1
℃
/W M
a x.
=
6 2
.
5
0
.
0 5
3 .
T
J M
–
T
C
=
P
D
* Z
θ
J
C
(
t)
M
0
.
0 2
1 0
0
0
.
0 1
P
DM
t
1
s in g le
pu ls e
t
2
1 0
–
1
1
0
–
4
1 0
–
3
1 0
–
2
1
0
–
1
1 0
0
1
0
1
1 0
2
t
1
, S
q u a
r
e
W a v e
P uls e
D u ra tio n
[s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Typical Characteristics : P-Channel
(Continued)
10
0
V
GS
10
0
Top :
-10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
-3.5 V
℃
150
Bottom :
-3.0 V
-1
10
℃
25
℃
-55
※
Notes :
μ
1. 250
s Pulse Test
※
Notes :
℃
2. T
C
= 25
-2
10
1. V
D
S
= -25V
μ
2. 250
s Pulse Test
-1
10
-1
10
10
0
10
1
0
2
4
6
8
10
-V
GS
, Gate-Source Voltage
[V]
-V
DS
,
D
rain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
30
25
20
15
10
10
0
V
G
S
= – 5V
V
G
S
= – 10V
℃
℃
25
150
※
Notes :
1. V
GS
= 0V
※
℃
Note : T = 25
J
μ
2. 250
s Pulse Test
-1
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.3
0.6
0.9
1.2
1.5
-I
D
, Drain Current
[A]
-V
SD
, Source-Drain Voltage
[V]
Figure 3. On-Resistance Variation
vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
250
200
150
100
50
12
10
8
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
oss
= C
ds
+ C
gd
rss
= C
gd
C
C
V
DS
= -60V
C
iss
V
DS
= -150V
6
V
DS
= -240V
C
oss
4
※
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
2
※
Note : I
D
= -0.3 A
5
0
10
0
-1
10
0
10
1
0
1
2
3
4
6
Q
G
, Total Gate Charge [nC]
V
DS
, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate
Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Typical Characteristics : P-Channel
(Continued)
1.2
1.1
1.0
2.5
2.0
1.5
1.0
0.5
0.0
※
N
otes :
1. V
G
S
= 0 V
0.9
※
Notes :
1. V
G
S
= -10 V
2. I
D
= -250
μ
A
2. I
D
= -0.1
5
A
0.8
-100
-100
-50
0
50
100
150
200
-50
0
50
100
150
200
T
J
, Junction Temperature [
o
C
]
T
J
, Junction Temperature [
o
C
]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
10
1
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Operation in This Area
is Limited by R
D
S(on)
10
0
1
m
s
10 ms
100 ms
1 s
-1
10
10 s
DC
-2
10
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
C
C
3. Single Pulse
-3
10
10
0
10
1
10
2
25
50
75
100
125
150
℃
T
C
, Case Temperature [
]
-V
DS
,
D
rain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case
Temperature
D = 0
.
5
0
.
2
1 0
1
※
N o
t
e s
1 .
Z
θ
J C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
0
.
1
℃
/W M
a x.
=
6 2
.
5
0
.
0 5
3 .
T
J M
–
T
C
=
P
D
* Z
θ
J
C
(
t)
M
0
.
0 2
1 0
0
0
.
0 1
P
DM
t
1
s in g le
pu ls e
t
2
1 0
–
1
1
0
–
4
1 0
–
3
1 0
–
2
1
0
–
1
1 0
0
1
0
1
1 0
2
t
1
, S
q u a
r
e
W a v e
P uls e
D u ra tio n
[s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Gate Charge Test Circuit & Waveform
V
GS
Same Type
50K
ꢀ
as DUT
Q
g
12V
200nF
5V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
5V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Package Dimensions
8-SOP
0.1~0.25
0.004~0.001
MIN
1.55
±
0.20
0.061
±
0.008
#8
#5
#1
#4
6.00
±
0.30
0.236
±
0.012
1.80
0.071
MAX
3.95
±
0.20
0.156
±
0.008
5.72
0.225
0.50
±
0.20
0.020
±
0.008
©2000 Fairchild Semiconductor International
Rev. A, August 2000
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
HiSeC™
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
Bottomless™
CoolFET™
CROSSVOLT™
E
2
CMOS™
FACT™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
®
QFET™
VCX™
FACT Quiet Series™
QS™
FAST
®
Quiet Series™
SuperSOT™-3
SuperSOT™-6
FASTr™
GTO™
DISCLAIMER
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
result in significant injury to the user.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. A,
January 2000
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FQS4900
Dual N-Channel 60V & P-Channel 300V
QFET
Contents
General description
|
Features
|
Product
status/pricing/packaging
General description
These N and P-Channel enhancement mode
power field effect transistors are produced
using Fairchild’s proprietary, planar stripe,
DMOS technology.
This advanced technology has been especially
tailored to minimize on-state resistance,
provide superior switching performance, and
withstand high energy pulse in the avalanche
and commutation mode. These devices are well
suited for low voltage applications such as high
efficiency switching DC/DC converters, and
DC motor control.
This page
Print version
Design tools
company
back to top
Features
●
●
●
N-Channel 1.3A, 60V,
R
= 0.55
Ω
@ V
= 10 V
GS
DS(on)
R
= 0.65
Ω
@ V
= 5 V
DS(on)
GS
P-Channel -0.3A, -300V,
R
= 15.5
Ω
@ V GS = -10 V
DS(on)
R
= 16
Ω
@ V
= -5 V
DS(on)
GS
Low gate charge
( typical N-Channel 1.6 nC)
(typical P- Channel 3.6nC)
Fast switching
●
●
Improved dv/dt capability
back to top
Product Folder – Fairchild P/N FQS4900 – Dual N-Channel 60V & P-Channel 300V QFET
Product status/pricing/packaging
Product
Product status
Pricing*
$0.46
Package type
Leads
Packing method
FQS4900TF
Full Production
SOIC
8
TAPE REEL
* 1,000 piece Budgetary Pricing
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