onsemi-HUF75345P3
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UltraFET
55
V
,
7
5 A, 7 m
W
HUF75345G3, HUF75345P3,
HUF75345S3S
Description
These N
−
Channel power MOSFETs are manufactured using
the innovative UltraFET process. This advanced process technology
achieves the lowest possible on
−
resistance per silicon area, resulting
in outstanding performance. This device is capable of withstanding
high energy in the avalanche mode and the diode exhibits very low
reverse recovery time and stored charge. It was designed for use
in applications where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay drivers,
low
−
voltage bus switches, and power management in portable
and battery
−
operated products.
V
R
MAX
I MAX
D
DSS
DS(ON)
55 V
7 m
W
75 A
D
G
S
Features
DRAIN (TAB)
•
75 A, 55 V
•
Simulation Models
TO
−
247
−
3
CASE 340CK
®
−
Temperature Compensated PSPICE
t
and SABER
Models
−
Thermal Impedance SPICE and SABER Models
•
Peak Current vs Pulse Width Curve
•
UIS Rating Curve
G
D
S
DRAIN (FLANGE)
TO
−
220
−
3
CASE 340AT
•
These Devices are Pb
−
Free
G
D
S
DRAIN (FLANGE)
D2PAK
−
3
CASE 418AJ
G
S
MARKING DIAGRAM
$Y&Z&3&K
75345X
$Y
= ON Semiconductor Logo
&Z
&3
&K
= Assembly Plant Code
= Data Code (
Y
e
ar & Week)
= Lot
75345X
= Specific Device Code
X = G/P/S
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
March, 2020
−
Rev. 3
HUF75345S3S/D
HUF75345G3, HUF75345P3, HUF75345S3S
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
HUF75345G3
HUF75345P3
HUF75345S3ST
Package
TO
−
247
−
3
TO
−
220
−
3
D2PAK
−
3
Brand
75345G
75345P
75345S
MOSFET MAXIMUM RATINGS
(T =
25
°
C, Unless otherwise noted)
C
Symbol
Parameter
Value
Unit
V
V
DSS
DGR
55
55
V
V
GS
V
GS
Gate to Source Voltage
20
V
I
Drain Current
−
Pulsed
75
A
D
I
Drain Current
325
DM
E
AS
Pulsed Avalanche Rating
Power Dissipation
P
(T =
25
°
C)
C
W
W/
°
C
°
C
D
−
Derate Above 25
°
C
2.17
T , T
Operating and Storage
T
e
mperature
−
55 to +175
300
J
STG
T
Maximum
T
e
mperature for Soldering Leads at 0.063 in (1.6 mm) from Case for 10 s
Maximum
T
e
mperature for Soldering Leads Package Body for 10 s
°
C
L
T
pkg
260
°
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. T =
25
°
C to 150
°
C
J
2
HUF75345G3, HUF75345P3, HUF75345S3S
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF STATE CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
55
V
DSS
D
GS
I
V
V
V
= 50 V, V
= 0 V
1
m
A
DSS
DS
DS
GS
GS
= 45
V
, V
= 0 V, T
=
1
50
_
C
250
100
GS
C
I
Gate to Source Leakage Current
=
20 V
nA
GSS
ON STATE CHARACTERISTICS
V
GS(TH)
R
DS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
2
4.0
V
GS
DS
D
I
D
0.006
0.007
W
GS
THERMAL CHARACTERISTICS
R
R
Thermal Resistance Junction to Ambient
TO
−
247
Thermal Resistance Junction to Ambient
TO
−
220, D2PAK
0.46
30
_
C/W
_
C/W
_
C/W
q
JC
JA
q
62
SWITCHING CHARACTERISTICS
(V =
10 V)
GS
t
Turn-On Time
Turn-On Delay Time
Rise Time
V
= 30
V, I
= 75
A,
195
ns
ns
ns
ns
ns
ns
ON
DD
L
D
R =
0.4
W
, V
= 10
V
, R
=
2
.5
W
GS
GS
t
14
118
42
d(ON)
t
r
t
Turn-Off Delay Time
Fall Time
d(OFF)
t
f
26
t
Turn-Off Time
98
OFF
GATE CHARGE CHARACTERISTICS
Q
Q
T
o
tal Gate Charge
V
V
g(REF)
= 0 V to 20
V
,
220
125
6.8
275
nC
nC
nC
g(tot)
g(10)
GS
DD
= 30
V
, I
=
7
5 A, R
= 0.4
W,
D
L
I
Gate Charge at 10 V
Threshold Gate Charge
V
V
g(REF)
= 0 V to 10
V
,
165
10
GS
DD
= 30
V
, I
=
7
5 A, R
= 0.4
W,
D
L
I
Q
V
V
g(REF)
= 0 V to 2
V
,
g(th)
GS
DD
= 30
V
, I
=
7
5 A, R
= 0.4
W,
D
L
I
Q
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
g(REF)
= 30
V
, I
=
7
5 A, R
= 0.4
W,
14
58
nC
nC
gs
DD
D
L
I
Q
gd
CAPACITANCE CHARACTERISTICS
C
Input Capacitance
V
= 25
V
, V
= 0 V, f = 1
M
hz
4000
1450
450
pF
pF
pF
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
rss
SOURCE TO DRAIN DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
Reverse Recovery Time
I
I
I
= 75 A
1.25
55
V
SD
SD
SD
SD
t
= 75 A, dl
/dt = 100 A/
m
s
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 75 A, dl
/dt = 100 A/
m
s
80
RR
SD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3
HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL PERFORMANCE CURVES
T
C
= 25
°
C unless otherwise noted
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
20
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
T
, CASE TEMPERATURE ( C)
C
o
T
, CASE TEMPERATURE (
C)
C
Figure 1. Normalized Power
Figure 2. Maximum Continuous
Dissipation vs. Case Temperature
Drain Current vs Case Temperature
2
DUTY CYCLE
−
DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
x Z
q
x R
+ T
q
JC C
J
DM
JC
SINGLE PULSE
0.01
10
−
5
−
4
−
3
−
2
−
1
10
0
1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
o
T
= 25
C
FOR TEMPERATURES
o
C
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175
−
T
C
I = I
25
150
V
= 20V
GS
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
−
5
10
−
4
−
3
−
2
10
−
1
0
1
10
10
10
10
10
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
4
HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL CHARACTERISTICS
(Continued)
T
C
= 25
°
C unless otherwise noted
NOTE: Refer
to ON Semiconductor Application Notes
1000
100
10
1000
100
If R = 0
= (L)(I
T
T
= MAX RATED
= 25
C
J
t
)/(1.3*RATED BV
AS DSS
−
V )
DD
AV
If R
ꢀ
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
o
C
t
−
V )
+1]
AV
AS
DSS
DD
100
m
s
o
STARTING T
= 25
C
1ms
J
10
1
OPERATION IN THIS
AREA MAY BE
10ms
o
STARTING T
= 150
C
J
LIMITED BY r
DS(ON)
V
= 55V
DSS(MAX)
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.01
0.1
1
10
, TIME IN AVALANCHE (ms)
AV
100
V
t
DS
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
150
150
120
PULSE DURATION = 80
m
s
V
= 20V
= 10V
= 7V
GS
DUTY CYCLE = 0.5% MAX
V
GS
120
90
V
GS
V
= 5V
GS
V
= 6V
GS
90
60
30
60
30
o
25 C
PULSE DURATION = 80
m
s
DUTY CYCLE = 0.5% MAX
C
o
175 C
o
−
55 C
o
V
= 15V
T
= 25
C
DD
0
0
0
1.5
V
3.0
4.5
6.0
7.5
0
1
2
3
4
V
, DRAIN TO SOURCE VOLTAGE (V)
, GATE TO SOURCE VOLTAGE (V)
DS
GS
Figure 7. Saturation Characteristics
Figure 8. Transfer Characteristics
2.5
1.2
1.0
PULSE DURATION = 80
m
s, V
= 10V, I
= 75A
V
= V
, I
= 250
m
A
DS
GS
D
GS
D
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
0.8
0.6
0.4
−
80
−
40
0
40
80
120
160
200
−
80
−
40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPERATURE (
C)
J
T ,
JUNCTION TEMPERATURE (
C)
J
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
5
HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL CHARACTERISTICS
(Continued)
T
C
= 25
°
C unless otherwise noted
1.3
7000
6000
5000
V
= 0V, f = 1MHz
GS
ISS
I
= 250
m
A
D
C
C
C
= C
= C
+ C
GS
GD
RSS
OSS
GD
1.2
1.1
C
+ C
GD
ꢁ
DS
C
ISS
4000
3000
1.0
0.9
0.8
2000
1000
0
C
C
OSS
RSS
0
10
V
20
30
40
50
60
−
80
−
40
0
40
80
120
o
160
200
, DRAIN TO SOURCE VOLTAGE (V)
DS
T ,
JUNCTION TEMPERATURE (
C)
J
Figure 11. Normalized Drain to Source
Breakdown vs. Junction Temperature
Figure 12. Capacitance vs. Drain to Source
Voltage
10
V
= 30V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
I
= 75A
= 55A
= 35A
= 20A
D
D
D
D
0
25
50
75
100
125
Q ,
GATE CHARGE (nC)
g
Figure 13. Gate Charge Waveforms
for Constant Gate Currents
6
HUF75345G3, HUF75345P3, HUF75345S3S
TEST CIRCUITS WAVEFORMS
V
DS
BV
DSS
t
P
V
L
DS
I
AS
VARY tp TO OBTAIN
REQUIRED PEAK I
V
DD
AS
R
G
+
V
DD
DUT
−
V
GS
tp
0 V
0
I
AS
t
AV
0.01
W
Figure 14. Unclamped Energy
Test Circuit
Figure 15. Unclamped Energy
Waveforms
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 20V
GS
Q
g(10)
V
GS
+
V
= 10V
V
GS
GS
V
DD
DUT
−
V
= 2V
GS
0
Q
I
g(REF)
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
V
GS
V
DD
−
10%
10%
0
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
Figure 18. Switching Time Test Circuit
Figure 19. Resistive Switching Waveforms
7
HUF75345G3, HUF75345P3, HUF75345S3S
PSPICE Electrical Model
.SUBCKT HUF75345 2 1 3 ; rev 3 Feb 99
CA 12 8 5.55e
−
9
CB 15 14 5.55e
−
9
CIN 6 8 3.45e
−
9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 56.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e
−
9
LG
A
T
E 1 9 2.6e
−
9
LSOURCE 3 7 1.1e
−
9
KG
A
T
E LSOURCE LG
A
T
E 0.0085
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e
−
4
RG
A
T
E 9 20 0.36
RLDRAIN 2 5 10
RLG
A
T
E 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e
−
6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.15e
−
3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VB
A
T
2
2 19 DC 1
ESLC 51 50
V
A
LUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e
−
6*500),3.5))}
.MODEL DBODYMOD D (IS = 6e
−
12 RS = 1.4e
−
3 IKF = 20 XTI = 5 TRS1 = 2.75e
−
3 TRS2 = 5.0e
−
6 CJO = 5.5e
−
9 TT =
5.9e
−
8 M = 0.5 VJ = 0.75)
.MODEL DBREAKMOD D (RS = 2.8e
−
2 IKF = 30 TRS1 =
−
4.0e
−
3 TRS2 = 1.0e
−
6)
.MODEL DPLCAPMOD D (CJO = 6.75e
−
9 IS = 1e
−
30 M = 0.88 VJ = 1.45 FC = 0.5)
.MODEL MMEDMOD NMOS (VTO = 2.93 KP = 13.75 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36)
.MODEL MSTROMOD NMOS (VTO = 3.23 KP = 96 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u Lambda = 0.06)
.MODEL MWEAKMOD NMOS (VTO = 2.35 KP =0.02 IS = 1e
−
30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL RBREAKMOD RES (TC1 = 8.0e
−
4 TC2 = 4.0e
−
6)
.MODEL RDRAINMOD RES (TC1 = 1.5e
−
1 TC2 = 6.5e
−
4)
8
HUF75345G3, HUF75345P3, HUF75345S3S
.MODEL RSLCMOD RES (TC1 = 1.0e
−
4 TC2 = 1.05e
−
6)
.MODEL RSOURCEMOD RES (TC1 = 1.0e
−
3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 =
−
1.5e
−
3 TC2 =
−
2.6e
−
5)
.MODEL RVTEMPMOD RES (TC1 =
−
2.75e
−
3 TC2 = 1.45e
−
6)
.MODEL S1AMOD VSWITCH (RON = 1e
−
5 ROFF = 0.1 VON =
−
9.00 VOFF=
−
4.00)
.MODEL S1BMOD VSWITCH (RON = 1e
−
5 ROFF = 0.1 VON =
−
4.00 VOFF=
−
9.00)
.MODEL S2AMOD VSWITCH (RON = 1e
−
5 ROFF = 0.1 VON = 0.00 VOFF= 0.50)
.MODEL S2BMOD VSWITCH (RON = 1e
−
5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult A New PSPICE Sub
−
Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
DBODY
RSLC1
DBREAK
51
+
RSLC2
ESLC
11
−
50
+
−
17
18
−
RDRAIN
6
EBREAK
MWEAK
ESG
8
EVTHRES
+
+
16
21
−
19
8
LGATE
EVTEMP
RGATE
GATE
1
6
+
−
18
MMED
22
9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S1B
S2A
14
13
S2B
RBREAK
12
15
13
8
17
18
RVTEMP
19
−
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 20. PSPICE Electrical Model
9
HUF75345G3, HUF75345P3, HUF75345S3S
SABER Electrical Model
REV 3 February 1999
template huf75345 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 6e
−
12, xti = 5, cjo = 5.5e
−
9, tt = 5.9e
−
8, m=0.5, vj=0.75)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 6.75e
−
9, is = 1e
−
30, m = 0.88, vj = 1.45,fc=0.5)
m..model mmedmod = (type=_n, vto = 2.93, kp = 13.75, is = 1e
−
30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.23, kp = 96, is=1e
−
30,tox=1,
lambda = 0.06)
m..model mweakmod = (type=_n, vto = 2.35, kp = 0.02, is = 1e
−
30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e
−
5, roff = 0.1, von =
−
9, voff =
−
4)
sw_vcsp..model s1bmod = (ron = 1e
−
5, roff = 0.1, von =
−
4, voff =
−
9)
sw_vcsp..model s2amod = (ron = 1e
−
5, roff = 0.1, von = 0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e
−
5, roff = 0.1, von = 0.5, voff = 0)
c.ca n12 n8 = 5.55e
−
9
c.cb n15 n14 = 5.55e
−
9
c.cin n6 n8 = 3.45e
−
9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e
−
9
l.lgate n1 n9 = 2.6e
−
9
l.lsource n3 n7 = 1.1e
−
9
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 8e
−
4, tc2 = 4e
−
6
res.rdbody n71 n5 = 1.4e
−
3, tc1 = 2.75e
−
3, tc2 = 5e
−
6
res.rdbreak n72 n5 = 2.8e
−
2, tc1 =
−
4e
−
3, tc2 = 1e
−
6
res.rdrain n50 n16 = 1e
−
4, tc1 = 1.5e
−
1, tc2 = 6.5e
−
4
res.rgate n9 n20 = 0.36
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e
−
6, tc1 = 1e
−
4, tc2 = 1.05e
−
6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.15e
−
3, tc1 = 1e
−
3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 =
−
2.75e
−
3, tc2 = 1.45e
−
6
res.rvthres n22 n8 = 1, tc1 =
−
1.5e
−
3, tc2 =
−
2.6e
−
5
spe.ebreak n11 n7 n17 n18 = 56.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
10
HUF75345G3, HUF75345P3, HUF75345S3S
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51
−
>n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e
−
9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3.5))
}
}
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
RDBODY
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
50
−
71
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
−
19
8
MWEAK
LGATE
EVTEMP
+
22
DBODY
RGATE
GATE
1
6
−
18
EBREAK
+
MMED
9
20
MSTRO
8
17
18
RLGATE
LSOURCE
CIN
−
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
−
+
+
VBAT
6
8
5
8
EGS
EDS
+
−
−
8
22
RVTHRES
Figure 21. SABER Electrical Model
11
HUF75345G3, HUF75345P3, HUF75345S3S
SPICE Thermal Model
REV 5 February 1999
HUF75345
th
JUNCTION
CTHERM1
RTHERM1
CTHERM1 th 6 6.3e
−
3
CTHERM2 6 5 1.5e
−
2
CTHERM3 5 4 2.0e
−
2
CTHERM4 4 3 3.0e
−
2
CTHERM5 3 2 8.0e
−
2
CTHERM6 2 tl 1.5e
−
1
6
CTHERM2
CTHERM3
CTHERM4
RTHERM1 th 6 5.0e
−
3
RTHERM2 6 5 1.8e
−
2
RTHERM3 5 4 5.0e
−
2
RTHERM4 4 3 8.5e
−
2
RTHERM5 3 2 1.0e
−
1
RTHERM6 2 tl 1.1e
−
1
RTHERM2
5
SABER Thermal Model
RTHERM3
SABER thermal model HUF75345
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.3e
−
3
ctherm.ctherm2 6 5 = 1.5e
−
2
ctherm.ctherm3 5 4 = 2.0e
−
2
ctherm.ctherm4 4 3 = 3.0e
−
2
ctherm.ctherm5 3 2 = 8.0e
−
2
ctherm.ctherm6 2 tl = 1.5e
−
1
4
3
2
RTHERM4
rtherm.rtherm1 th 6 = 5.0e
−
3
rtherm.rtherm2 6 5 = 1.8e
−
2
rtherm.rtherm3 5 4 = 5.0e
−
2
rtherm.rtherm4 4 3 = 8.5e
−
2
rtherm.rtherm5 3 2 = 1.0e
−
1
rtherm.rtherm6 2 tl = 1.1e
−
1
}
CTHERM5
CTHERM6
RTHERM5
RTHERM6
tl
CASE
Figure 22. Thermal Model
PSPICE is a trademark
of MicroSim Corporation.
Saber is a registered trademark of
Sabremark Limited Partnership
.
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
220
−
3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO
−
220
−
3LD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
247
−
3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM
MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
=
Y
e
ar
WW =
Work Week
ZZ =
Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO
−
247
−
3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D
2
PAK
−
3 (TO
−
263, 3
−
LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
=
Y
e
ar
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb
−
Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D
2
PAK
−
3 (TO
−
263, 3
−
LEAD)
PAGE 1 OF 1
DESCRIPTION:
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
onsemi
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