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HUF76143P3, HUF76143S3S
Data Sheet
January 2003
75A, 30
V
,
0
.0055 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
Features
• Logic
Level Gate Drive
• 75A,
30V
These N-Channel power MOSFETs
are manufactured using the
• Ultra
Low On-Resistance, r
= 0.0055
Ω
innovative UltraFET™ process.
DS(ON)
®
This advanced process technology
•
T
e
mperature
Compensating PSPICE
Model
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
©
•
T
e
mperature
Compensating SABER
Mode
• Thermal
Impedance SPICE Model
• Thermal
Impedance SABER Model
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
• Related
Literature
– TB334,
“Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type
T
A
76143.
Ordering Information
Symbol
D
PART NUMBER
PACKAGE
TO-220AB
TO-263AB
BRAND
76143P
76143S
HUF76143P3
G
HUF76143S3S
NOTE: When
ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76143S3S
T
.
S
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
DRAIN
(FLANGE)
SOURCE
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
o
Absolute Maximum Ratings
T =
25 C,
Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
V
V
V
DSS
Drain to Gate
V
o
ltage (R
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±
20
GS
Drain Current
o
Continuous (T
= 25
C, V
C
= 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
75
75
75
A
A
A
GS
D
D
o
Continuous (T
= 100
C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
o
Continuous (T
= 100
C, V
C
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Ratin
g
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E
Figure 6
AS
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P
Derate Above 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
1.8
W
W/ C
D
o
o
o
Operating and Storage
T
emperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T ,
T
J
-40 to 150
C
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
= 250
µ
A, V
= 0V (Figure 12)
30
–
–
–
–
–
–
V
D
GS
GS
GS
I
V
V
V
= 25V, V
= 25V, V
=
±
20V
= 0V
1
µ
A
µ
A
nA
DSS
DS
DS
GS
o
= 0V, T
= 150
C
–
250
±
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
–
GSS
V
V
= V
, I
= 250
µ
A (Figure 11)
1
–
–
3
V
GS(TH)
GS
DS
D
GS
GS
GS
r
I
I
I
= 75A, V
= 75A, V
= 75A, V
= 10V (Figures 9, 10)
= 5V (Figure 9)
0.0052
0.0063
0.0068
0.0055
0.0075
0.0085
Ω
Ω
Ω
DS(ON)
D
D
D
–
= 4.5V (Figure 9)
–
THERMAL SPECIFICATIONS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-220 and TO-263
–
–
–
–
0.55
62
C/W
θ
JC
o
C/W
θ
JA
SWITCHING SPECIFICATIONS
(V
Turn-On Time
= 4.5V)
GS
t
V
R
R
= 15V, I
75A,
=
4.5V,
–
–
–
–
–
–
–
22
145
30
18
–
250
ns
ns
ns
ns
ns
ns
ON
DD
L
D
= 0.2
Ω
, V
GS
Turn-On Delay Time
Rise Time
t
–
–
d(ON)
= 2.5
Ω
GS
t
r
Turn-Off Delay Time
Fall Time
t
–
d(OFF)
t
–
f
Turn-Off Time
t
72
OFF
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
o
Electrical Specifications
T
= 25
C, Unless Otherwise Specified
(Continued)
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
(V
Turn-On Time
= 10V)
GS
t
V
R
R
= 15V, I
75A,
= 10V,
–
–
–
–
–
–
–
105
ns
ns
ns
ns
ns
ns
ON
DD
L
D
= 0.2
Ω
, V
GS
Turn-On Delay Time
Rise Time
t
14
55
40
18
–
–
–
d(ON)
= 2.5
Ω
GS
(Figures 16, 21, 20)
t
r
Turn-Off Delay Time
Fall Time
t
–
d(OFF)
t
–
f
Turn-Off Time
t
87
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
DD
= 15V,
75A,
–
–
–
–
–
95
50
114
60
4.6
–
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 5V
Q
g(5)
R =
0.2
Ω
L
I
= 1.0mA
g(REF)
(Figures 14, 19, 20)
Threshold Gate Charge
Q
3.8
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
11.70
22.00
gs
gd
Q
–
C
V
= 25V, V
= 0V,
GS
–
–
–
3900
1600
270
–
–
–
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
90
UNITS
V
V
I
I
I
= 75A
–
–
–
–
–
–
SD
SD
SD
SD
t
= 75A, dI
/dt = 100A/
µ
s
SD
ns
rr
Reverse Recovered Charge
Q
= 75A, dI
/dt = 100A/
µ
s
170
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
V
= 10V
GS
40
20
V
= 4.5V
GS
10
25
50
75
100
125
150
0
25
50
75
100
125
150
o
o
T ,
AMBIENT TEMPERATURE (
C)
T ,
CASE TEMPER
A
T
URE (
C)
A
C
FIGURE 1.
NORMALIZED POWER DISSI
P
ATION vs CASE
TEMPER
A
TURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
(Continued)
2
1
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY
F
ACTOR: D = t
/t
SINGLE PULSE
1
2
PEAK T
= P
DM
x Z
x R
+ T
θ
JC C
J
θ
JC
0.01
-5
10
-4
-3
10
-2
10
-1
0
1
10
10
10
10
t, REC
T
A
NGULAR PULSE DURATION (s)
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
o
T
= 25
C
C
FOR TEMPER
A
T
URES
ABOVE 25
C DER
A
T
E PEAK
1000
o
CURRENT AS FOLLOWS:
150 – T
125
C
I = I
25
V
= 5V
GS
V
= 10V
GS
100
50
TRANSCONDUC
T
A
NCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
10
t, PULSE WIDTH (s)
FIGURE 4.
PEAK CURRENT CA
P
A
BILITY
500
If R = 0
1000
t =
(L)(I )/(1.3*R
A
T
ED
BV
AV
– V
)
DD
T
T
= MAX RATED
= 25
C
AS
DSS
J
o
If R
≠
0
C
t
AV
= (L/R)ln[(I
*R)/(1.3*RATED BV
AS
– V
) +1]
DD
DSS
100
µ
s
100
10
1
100
o
S
T
A
RTING T
= 25
C
J
1ms
10ms
o
STARTING T
= 150
C
J
OPERATION IN THIS
AREA M
A
Y
B
E
LIMITED BY r
DS(ON)
10
0.001
BV
DSS MAX
= 30V
0.01
0.1
1
10
100
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
t
, TIME IN AVALANCHE (ms)
AV
V
DS
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING CA
P
A
BILITY
FIGURE 5.
FORWARD BIAS SAFE OPERATING AREA
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
(Continued)
200
150
100
50
200
150
100
50
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= 10V
GS
V
= 15V
DD
V
= 5V
= 4V
GS
V
GS
V
= 3.5V
GS
o
V
= 3V
GS
150 C
o
25 C
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
-40 C
o
T
= 25
C
3
C
0
0
0
1
2
3
4
5
0
1
2
4
5
V
, G
A
T
E TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7.
TRANSFER CHARACTERISTICS
FIGURE 8.
SATURATION CHARACTERISTICS
15
2
1.6
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
I
= 75A
D
V
= 10
V
, I
=
7
5A
GS
D
I
= 50A
1.4
D
1.2
1.0
0.8
0.7
9
6
I =
25A
D
3
-60
0
60
120
o
180
2
4
6
8
10
V
, G
A
T
E TO SOURCE VOLTAGE (V)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
FIGURE 9.
SOURCE TO DRAIN ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10.
NORMALIZED DRAIN TO SOURCE ON
RESIS
T
A
NCE vs JUNCTION TEMPERATURE
1.2
1.2
I
= 250
µ
A
V
= V
, I
= 250
µ
A
DS D
D
GS
1.0
0.8
0.6
0.5
1.1
1.0
0.9
-60
0
60
120
o
180
-60
0
60
120
o
180
T ,
JUNCTION TEMPER
A
T
URE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 11.
NORMALIZED GATE THRESHOLD VO
L
TAGE vs
JUNCTION TEMPER
A
T
URE
FIGURE 12.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Typical Performance Curves
(Continued)
10
8
5000
4000
3000
2000
1000
0
C
ISS
V
= 0
V
, f =
1
MHz
GS
ISS
6
C
C
C
= C
+ C
GS
GD
= C
RSS
OSS
GD
DS GD
≈
C
+ C
4
C
WAVEFORMS IN
DESCENDING ORDER:
OSS
I
I
I
= 75A
= 50A
= 25A
2
D
D
D
C
RSS
V
= 15V
DD
0
0
20
40
60
80
100
0
5
10
15
20
25
30
Q ,
G
A
T
E CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
g
DS
NOTE: Refer
to Fairchild Application Notes 7254 and 7260.
FIGURE 14.
GATE CHARGE WAVEFORMS FOR CONSTANT
G
A
TE CURRENT
FIGURE 13.
CA
P
A
CITANCE vs DRAIN TO SOURCE VOLTAGE
800
800
V
= 4.5
V
, V
=
1
5
V
,
I =
7
5A, R
= 0.2
Ω
DD D
L
V
= 10
V
, V
DD
= 15
V
,
I =
7
5A, R
= 0.2
Ω
GS
GS
D
L
600
400
200
0
600
400
200
0
t
d(OFF)
t
r
t
d(OFF)
t
f
t
f
t
r
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, G
A
T
E TO SOURCE RESISTANCE (
Ω
)
R
, GATE TO SOURCE RESISTANCE (
Ω
)
GS
GS
FIGURE 15.
SWITCHING TIME vs G
A
TE RESISTANCE
FIGURE 16.
SWITCHING TIME vs G
A
TE RESISTANCE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
–
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 17.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18.
UNCLAMPED ENERGY W
A
VEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
Test Circuits and Waveforms
(Continued)
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(5)
+
–
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
I
gREF)
0
FIGURE 19.
GATE CHARGE TEST CIRCUIT
FIGURE 20.
GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21.
SWITCHING TIME TEST CIRCUIT
FIGURE 22.
SWITCHING TIME WAVEFORM
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
PSPICE Electrical Model
SUBCKT HUF76143 2 1 3 ;
REV March 1998
CA 12 8
5.2e-9
CB 15 14
5e-9
CIN 6 8
3.65e-9
LDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
+
DBREAK
EBREAK 11 7 17
18 39.38
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
RSLC2
5
ESLC
11
51
–
50
+
–
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
–
EVTHRES
+
+
16
21
IT 8 17 1
–
19
8
MWEAK
LG
A
T
E
EVTEMP
RG
A
T
E
G
A
T
E
1
LDRAIN 2 5 1e-9
LGATE 1
9 2.6e-9
LSOURCE 3 7
1.1e-9
6
+
–
18
22
MMED
9
20
MSTRO
8
RLG
A
T
E
LSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.5e-3
RGATE 9 20
0.92
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
3e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
–
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
RVTHRES
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*425),4))}
.MODEL DBODYMOD D (IS = 1.2e-11
RS = 2.65e-3
TRS1 = 2.3e-3
TRS2 = -4.2e-6
CJO = 5.45e-9
TT = 3.9e-8 XTI = 4.3 N = 1.03 M = 0.43)
.MODEL DBREAKMOD D (RS = 8.5e-2
TRS1 =0
TRS2 =0)
.MODEL DPLCAPMOD D (CJO = 2.6e-9
IS = 1e-30
N = 10 M = 0.7)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.92)
.MODEL MSTROMOD NMOS (VTO = 2.26KP = 215 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.8e-4
TC2 = -4e-7)
.MODEL RDRAINMOD RES (TC1 = 1e-2
TC2 = 0)
.MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = -2e-5)
.MODEL RSOURCEMOD RES (TC1 = 5e-4 TC2 = 1.1e-5)
.MODEL RVTHRESMOD RES (TC = -2.2e-3 TC2 = -6e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.45e-3
TC2 = -2e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -5
VOFF= -2)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -2
VOFF= -5)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -1.5
VOFF= 1)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 1
VOFF= -1.5)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatle
y
.
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
SABER Electrical Model
REV March 1998
template huf76143 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod =
(is = 1.2e-11, xti = 4.3, cjo = 5.45e-9, tt = 3.9e-8, n = 1.03, m = 0.43)
d..model dbreakmod = ()
d..model dplcapmod =
(cjo = 2.6e-9, is = 1e-30, n = 10, m = 0.70)
m..model mmedmod = (type=_n, vto = 1.9, kp = 10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.26, kp = 215, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod =
(ron = 1e-5, roff = 0.1, von = -5, voff = -2)
sw_vcsp..model s1bmod =
(ron = 1e-5, roff = 0.1, von = -2, voff = -5)
sw_vcsp..model s2amod =
(ron = 1e-5, roff = 0.1, von = -1.5, voff = 1)
sw_vcsp..model s2bmod =
(ron = 1e-5, roff = 0.1, von = 1, voff = -1.5)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 5.2e-9
c.cb n15 n14 = 5e-9
c.cin n6 n8 = 3.65e-9
RSLC2
ISCL
50
–
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
–
19
8
i.it n8 n17 = 1
MWEAK
LG
A
T
E
EVTEMP
DBODY
RG
A
T
E
G
A
T
E
1
6
+
–
18
22
EBREAK
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9
l.lsource n3 n7 = 1.1e-9
MMED
9
20
MSTRO
8
17
18
–
RLG
A
T
E
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
7
RSOURCE
RLSOURCE
S1A
12
S2A
res.rbreak n17 n18
= 1, tc1 = 9.8e-4, tc2 = -4e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 2.3e-3, tc2 = -4.2e-6
res.rdbreak n72 n5 = 8.5e-2, tc1 = 0, tc2 = 0
res.rdrain n50 n16
= 1.5e-3, tc1 = 1e-2, tc2 = 0
res.rgate n9 n20 = 0.92
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51
= 1e-6, tc1 = 3e-3, tc2 = -2e-5
res.rslc2 n5 n50 = 1e3
RBREAK
15
13
8
14
13
17
18
RVTEMP
19
–
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
res.rsource n8 n7
= 3e-3, tc1 = 5e-4, tc2 = 1.1e-5
res.rvtemp n18 n19
= 1, tc1 = -1.45e-3, tc2 = -2e-6
res.rvthres n22 n8
= 1, tc1 = -2.2e-3, tc2 = -6e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 39.38
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/425))** 4))
}
}
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
HUF76143P3, HUF76143S3S
SPICE Thermal Model
JUNCTION
th
REV March 1998
HUF76143
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 5.0e-3
CTHERM2 6 5 1.2e-2
CTHERM3 5 4 2.0e-2
CTHERM4 4 3 2.8e-2
CTHERM5 3 2 2e-1
CTHERM6 2 tl 3
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 2.0e-3
RTHERM2 6 5 2.0e-2
RTHERM3 5 4 6.9e-2
RTHERM4 4 3 1.3e-1
RTHERM5 3 2 7.5e-2
RTHERM6 2 tl 3.0e-2
5
SABER Thermal Model
Saber thermal model HUF76143
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.2e-2
ctherm.ctherm3 5 4 = 2.0e-2
ctherm.ctherm4 4 3 = 2.8e-2
ctherm.ctherm5 3 2 = 2.0e-1
ctherm.ctherm6 2 tl = 3
rtherm.rtherm1 th 6 = 2.0e-3
rtherm.rtherm2 6 5 = 2.0e-2
rtherm.rtherm3 5 4 = 6.9e-2
rtherm.rtherm4 4 3 = 1.3e-1
rtherm.rtherm5 3 2 = 7.5e-2
rtherm.rtherm6 2 tl = 3.0e-2
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
HUF76143P3, HUF76143S3S Rev. B1
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Formative or In
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.
Rev. I2
