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HUFA75329G3, HUFA75329P3, HUFA75329S3S
Data Sheet
June 2002
49A, 55
V
,
0
.024 Ohm, N-Channel UltraFET
Power MOSFETs
Features
• 49A,
55V
These N-Channel power MOSFETs
are manufactured using the
•
Ultra Low On-Resistance
, r
= 0.024
Ω
DS(ON)
•
T
e
mperature
Compensating PSPICE® and SABER™
Models
innovative UltraFET® process. This
advanced process technology
• Thermal
Impedance PSPICE and SABER Models
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Related
Literature
– TB334,
“Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type
T
A
75329.
D
Ordering Information
PART NUMBER
HUFA75329G3
HUFA75329P3
HUFA75329S3S
PACKAGE
BRAND
75329G
TO-247
G
TO-220AB
TO-263AB
75329P
75329S
S
NOTE: When
ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75329S3S
T
.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
G
A
T
E
SOURCE
DRAIN
G
A
T
E
DRAIN
(FLANGE)
DRAIN
(TAB)
JEDEC TO-263AB
DRAIN
(FLANGE)
G
A
T
E
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
o
Absolute Maximum Ratings
T
= 25
C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1
)
. . . . . . . . . . . . . . . . . . . . . . . V
55
55
V
V
V
DSS
Drain to Gate
V
o
ltage (R
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
Drain Current
±
20
GS
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
49
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
I
Figure 4
DM
Pulsed Avalanche Ratin
g
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E
Figures 6, 14, 15
AS
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P
128
0.86
W
D
o
o
Derate Above 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage
T
emperature . . . . . . . . . . . . . . . . . .T
, T
-55 to 175
C
J
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250
µ
A, V
= 0V (Figure 11)
55
–
–
–
–
–
–
V
DSS
D
GS
GS
GS
I
V
V
V
= 50V, V
= 45V, V
=
±
20V
= 0V
= 0V, T
= 150
C
1
µ
A
µ
A
nA
DSS
DS
DS
GS
o
–
250
±
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
–
GSS
V
V
= V
, I
= 250
µ
A (Figure 10)
2
–
–
4
V
GS(TH)
GS
DS
D
r
I
= 49A, V
= 10V (Figure 9)
0.020
0.024
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-247
–
–
–
–
–
–
1.17
30
C/W
θ
JC
o
C/W
θ
JA
o
TO-220, TO-263
62
C/W
SWITCHING SPECIFICATIONS
(V
Turn-On Time
= 10V)
GS
t
V
R
R
= 30V, I
D
49A,
=
10V,
–
–
–
–
–
–
–
105
ns
ns
ns
ns
ns
ns
ON
DD
L
= 0.61
Ω
, V
GS
Turn-On Delay Time
Rise Time
t
12
58
33
33
–
–
d(ON)
= 9.1
Ω
GS
t
–
r
Turn-Off Delay Time
Fall Time
t
–
–
d(OFF)
t
f
Turn-Off Time
t
100
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
49A,
–
–
–
–
–
60
35
2.0
5
75
43
2.5
–
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 10V
Q
g(10)
R =
0.61
Ω
L
I
= 1.0mA
Threshold Gate Charge
Q
g(REF)
(Figure 13)
g(TH)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q
gs
gd
Q
13
–
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
o
Electrical Specifications
T
= 25
C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
V
= 25V, V
DS GS
= 0V,
–
–
–
1060
405
95
–
–
–
pF
pF
pF
ISS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
72
UNITS
V
V
I
I
I
= 49A
–
–
–
–
–
–
SD
SD
SD
SD
t
= 49A, dI
/dt = 100A/
µ
s
SD
ns
rr
Reverse Recovered Charge
Q
= 49A, dI
/dt = 100A/
µ
s
120
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
60
50
40
30
20
10
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPERATURE (
C)
C
C
FIGURE 1.
NORMALIZED POWER DISSI
P
ATION vs CASE
TEMPER
A
TURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
x Z
x R
+ T
θ
JC C
J
DM
θ
JC
SINGLE PULSE
0.01
-5
-4
10
-3
10
-2
-1
10
0
1
10
10
t,
R
ECTANGULAR PULSE DURATION (s)
10
10
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Typical Performance Curves
(Continued)
1000
100
10
o
T
= 25
C
FOR TEMPER
A
T
URES
ABOVE 25
C DERATE PEAK
C
o
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
V
= 10V
GS
TRANSCONDUC
T
A
NCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
-5
10
-4
-3
-2
-1
0
1
10
10
10
t,
P
ULSE WIDTH (s)
10
10
10
FIGURE 4.
PEAK CURRENT CA
P
A
BILITY
500
If R = 0
t
= (L)(I
)/(1.3*R
A
T
ED BV
– V
)
500
100
AV
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*R
A
T
ED BV
AS
DSS
DD
T
= MAX R
A
T
ED
o
J
t
– V
) +1]
DD
T
= 25
C
AV
AS DSS
C
100
100
µ
s
o
STARTING T
= 25
C
J
10
1
1ms
o
S
T
A
RTING T
= 150
C
J
OPER
A
T
ION IN THIS
AREA M
A
Y
B
E
10ms
LIMITED BY r
DS(ON)
= 55V
V
DSS(MAX)
10
0.001
0.01
0.1
1
10
t
, TIME IN AVALANCHE (ms)
1
10
100
200
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING CA
P
A
BILITY
100
80
60
40
20
0
100
V
= 20V
= 10V
= 8V
PULSE TEST
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
GS
o
-55 C
V
GS
V
V
GS
= 7V
80
GS
V
= 6V
GS
o
175 C
60
40
20
V
GS
= 5V
PULSE DURATION = 80
µ
s
o
T
= 25
C
o
V
= 15V
C
25 C
DD
0
0
1
2
3
4
5
0
1.5
3.0
4.5
6.0
7.5
V ,
DRAIN TO SOURCE VOLTAGE (V)
DS
V
, G
A
T
E TO SOURCE VOLTAGE (V)
GS
FIGURE 7.
SATURATION CHARACTERISTICS
FIGURE 8.
TRANSFER CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Typical Performance Curves
(Continued)
2.5
2.0
1.5
1.0
0.5
1.2
1.0
0.8
0.6
0.4
80
µ
s PULSE TEST
= 10
V
, I
=
4
9A
V
= V
, I
= 250
µ
A
DS
GS
D
V
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPER
A
T
URE (
C)
T ,
JUNCTION TEMPER
A
T
URE (
C)
J
J
FIGURE 9.
NORMALIZED DRAIN TO SOURCE ON
FIGURE 10.
NORMALIZED GATE THRESHOLD VO
L
TAGE vs
JUNCTION TEMPER
A
T
URE
RESIS
T
A
NCE vs JUNCTION TEMPERATURE
1.2
1.1
1.0
0.9
0.8
1800
V
= 0
V
, f =
1
MHz
I
= 250
µ
A
GS
ISS
D
C
C
C
= C
+ C
GS
GD
1500
1200
900
600
300
0
= C
RSS
OSS
GD
DS GD
≈
C
+ C
C
ISS
C
C
OSS
RSS
-80
-40
0
40
80
120
160
200
0
10
20
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
40
50
60
o
T ,
JUNCTION TEMPERATURE (
C)
V
J
FIGURE 11.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12.
CA
P
A
CI
T
A
NCE vs DRAIN TO SOURCE VO
L
TAGE
10
8
6
4
WA
V
EFORMS IN
DESCENDING ORDER:
I
I
I
I
= 49A
D
D
D
D
2
= 36.75A
= 24.5A
= 12.25A
V
= 30V
DD
0
0
5
10
15
20
25
30
35
Q ,
G
A
T
E CHARGE (nC)
g
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13.
GATE CHARGE WAVEFORMS FOR CONS
T
A
NT G
A
TE CURRENT
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
–
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 14.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15.
UNCLAMPED ENERGY W
A
VEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
–
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16.
GATE CHARGE TEST CIRCUIT
FIGURE 17.
G
A
TE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18.
SWITCHING TIME TEST CIRCUIT
FIGURE 19.
RESISTIVE SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
PSPICE Electrical Model
.SUBCKT HU
F
A
75329P 2 1 3 ;
rev 6/18/02
CA 12 8
1.72e-9
CB 15 14
1.52e-9
CIN 6 8
9.61e-10
LDRAIN
DPLCAP
DRAIN
2
5
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
EBREAK 11 7 17 18 58.13
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
5
ESLC
11
51
–
50
+
–
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
–
EVTHRES
+
+
16
21
–
19
8
MWEAK
IT 8 17 1
LG
A
T
E
EVTEMP
RG
A
T
E
G
A
T
E
1
6
+
–
18
22
LDRAIN 2 5 1e-9
LGATE 1
9 2.86e-9
LSOURCE 3 7
2.69e-9
MMED
9
20
MSTRO
8
RLG
A
T
E
LSOURCE
CIN
SOURCE
3
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20
1.52
RBREAK
12
15
13
8
14
13
17
18
RLDRAIN 2 5 10
RLGATE 1 9 26.9
RLSOURCE 3 7 28.6
RSLC1 5 51 RSLCMOD 1e-6
RVTEMP
19
–
S1B
S2B
13
CB
CA
IT
14
+
+
RSLC2 5 50 1e3
VBAT
6
8
5
8
EGS
EDS
RSOURCE 8 7 RSOURCEMOD
13.85e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
+
–
–
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}
.MODEL DBODYMOD D (IS = 7.50e-13
RS = 5.05e-3
TRS1 = 2.21e-3
TRS2 = 1.02e-6
CJO = 1.51e-9
TT = 4.05e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.14e-1
TRS1 = 9.62e-4
TRS2 = 1.23e-6)
.MODEL DPLCAPMOD D (CJO = 13.5e-10
IS = 1e-30
N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)
.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3
TC2 = 1.94e-7)
.MODEL RDRAINMOD RES (TC1 = 8.04e-2
TC2 = 1.37e-4)
.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.35e-3
TC2 = 1.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -7.90 VOFF= -4.90)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -4.90 VOFF= -7.90)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -0.50 VOFF= 2.50)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 2.50 VOFF= -0.50)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatle
y
.
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
SABER Electrical Model
REV June 2002
template hufa75329p n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod =
(is = 7.50e-13, cjo = 1.51e-9, tt = 4.05e-8, m = 0.5)
d..model dbreakmod = ()
d..model dplcapmod =
(cjo = 13.5e-10, is = 1e-30, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.50, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.80, kp = 70, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.06, is = 1e-30, tox = 1)
sw_vcsp..model s1amod =
(ron = 1e-5, roff = 0.1, von = -7.90, voff = -4.90)
sw_vcsp..model s1bmod =
(ron = 1e-5, roff = 0.1, von = -4.90, voff = -7.90)
sw_vcsp..model s2amod =
(ron = 1e-5, roff = 0.1, von = -0.50, voff = 2.50)
sw_vcsp..model s2bmod =
(ron = 1e-5, roff = 0.1, von = 2.50, voff = -0.50)
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RDBODY
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
c.ca n12 n8 = 1.72e-9
c.cb n15 n14 = 1.52e-9
c.cin n6 n8 = 9.61e-10
50
–
71
RDRAIN
6
8
ESG
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
EVTHRES
+
16
21
+
–
19
8
MWEAK
LG
A
T
E
EVTEMP
DBODY
RG
A
T
E
GATE
1
6
+
–
18
22
EBREAK
+
MMED
i.it n8 n17 = 1
9
20
MSTRO
8
17
18
–
RLGATE
l.ldrain n2 n5 = 1e-9
LSOURCE
CIN
l.lgate n1 n9 = 2.86e-9
l.lsource n3 n7 = 2.69e-9
SOURCE
3
7
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
res.rbreak n17 n18
= 1, tc1 = 1.05e-3, tc2 = 1.94e-7
res.rdbody n71 n5 = 5.05e-3, tc1 = 2.21e-3, tc2 = 1.02e-6
res.rdbreak n72 n5 = 2.14e-1, tc1 = 9.62e-4, tc2 = 1.23e-6
res.rdrain n50 n16
= 1e-3, tc1 = 8.04e-2, tc2 = 1.37e-4
res.rgate n9 n20 = 1.52
13
CB
CA
IT
14
–
+
+
VB
A
T
6
8
5
8
EGS
EDS
+
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26.9
–
–
8
22
res.rlsource n3 n7 = 28.6
RVTHRES
res.rslc1 n5 n51
= 1e-6, tc1 = 4.83e-3, tc2 = 1.16e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 13.85e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19
= 1, tc1 = -1.35e-3, tc2 = 1.16e-6
res.rvthres n22 n8
= 1, tc1 = -3.43e-3, tc2 = -1.63e-5
spe.ebreak n11 n7 n17 n18 = 58.13
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/135))** 3.5))
}
}
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
HUFA75329G3, HUFA75329P3, HUFA75329S3S
SPICE Thermal Model
JUNCTION
th
REV 18June2002
HUFA75329P
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM1 th 6 2.80e-3
CTHERM2 6 5 1.00e-2
CTHERM3 5 4 6.80e-3
CTHERM4 4 3 7.00e-3
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 5.1e-2
6
RTHERM1 th 6 7.94e-3
RTHERM2 6 5 1.98e-2
RTHERM3 5 4 5.57e-2
RTHERM4 4 3 3.13e-1
RTHERM5 3 2 4.61e-1
RTHERM6 2 tl 7.26e-2
5
SABER Thermal Model
SABER thermal model HUFA75329P
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.80e-3
ctherm.ctherm2 6 5 = 1.00e-2
ctherm.ctherm3 5 4 = 6.80e-3
ctherm.ctherm4 4 3 = 7.00e-3
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 5.1e-2
rtherm.rtherm1 th 6 = 7.94e-3
rtherm.rtherm2 6 5 = 1.98e-2
rtherm.rtherm3 5 4 = 5.57e-2
rtherm.rtherm4 4 3 = 3.13e-1
rtherm.rtherm5 3 2 = 4.61e-1
rtherm.rtherm6 2 tl = 7.26e-2
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
HUFA75329G3, HUFA75329P3, HUFA75329S3S Rev. A
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Advance Information
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Rev. H7
