onsemi-HUFA75332S3S
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HUFA75332G3, HUFA75332P3, HUFA75332S3S
Data Sheet
June 2002
60A, 55
V
,
0
.019 Ohm, N-Channel UltraFET
Power MOSFETs
Features
• 60A,
55V
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
• Simulation
Models
–
T
e
mperature
Compensated PSPICE® and SABER™
Models
advanced process technology
– SPICE
and SABER Thermal Impedance Models
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
• Related
Literature
– TB334,
“Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type
T
A
75332.
D
Ordering Information
PART NUMBER
HUFA75332G3
HUFA75332P3
HUFA75332S3S
PACKAGE
BRAND
75332G
G
TO-247
TO-220AB
TO-263AB
75332P
75332S
S
NOTE: When
ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75332S3S
T
.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
G
A
T
E
SOURCE
DRAIN
G
A
T
E
DRAIN
(FLANGE)
DRAIN
(TAB)
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
o
Absolute Maximum Ratings
T
= 25
C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1
)
. . . . . . . . . . . . . . . . . . . . . . . V
55
55
V
V
V
DSS
Drain to Gate
V
o
ltage (R
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
Drain Current
±
20
GS
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
60
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
I
Figure 4
Figure 6
DM
Pulsed Avalanche Ratin
g
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E
AS
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P
145
0.97
W
D
o
o
Derate Above 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W/ C
o
Operating and Storage
T
emperature . . . . . . . . . . . . . . . . . .T
, T
-55 to 175
C
J
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . T
Package Body for 10s, See
T
e
chbrief 334 . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T
= 25
C to 150
C.
J
o
Electrical Specifications
T =
25 C,
Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250
µ
A, V
= 0V (Figure 11)
55
–
–
–
–
–
–
V
DSS
D
GS
GS
GS
I
V
V
V
= 50V, V
= 45V, V
=
±
20V
= 0V
= 0V, T
= 150
C
1
µ
A
µ
A
nA
DSS
DS
DS
GS
o
–
250
±
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
–
GSS
V
V
= V
, I
= 250
µ
A (Figure 10)
2
–
–
4
V
GS(TH)
GS
DS
D
r
I
= 60A, V
= 10V (Figure 9)
0.016
0.019
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-247
–
–
–
–
–
–
1.03
30
C/W
θ
JC
o
C/W
θ
JA
o
TO-220, TO-263
62
C/W
SWITCHING SPECIFICATIONS
(V
Turn-On Time
= 10V)
GS
t
V
R
R
= 30V, I
D
60A,
=
10V,
–
–
–
–
–
–
–
100
ns
ns
ns
ns
ns
ns
ON
DD
= 0.50
Ω
, V
L
GS
Turn-On Delay Time
Rise Time
t
12
55
11
25
–
–
–
d(ON)
= 6.8
Ω
GS
t
r
Turn-Off Delay Time
Fall Time
t
–
d(OFF)
t
–
f
Turn-Off Time
t
55
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
60A,
–
–
–
–
–
70
40
2.5
6
85
50
3.0
–
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 10V
Q
g(10)
R =
0.50
Ω
L
I
= 1.0mA
Threshold Gate Charge
Q
g(REF)
(Figure 13)
g(TH)
Gate to Source Gate Charge
Reverse Transfer Capacitance
Q
gs
gd
Q
15
–
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
o
Electrical Specifications
T
= 25
C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
V
= 25V, V
DS GS
= 0V,
–
–
–
1300
480
–
–
–
pF
pF
pF
ISS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
115
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
75
UNITS
V
V
I
I
I
= 60A
–
–
–
–
–
–
SD
SD
SD
SD
t
= 60A, dI
/dt = 100A/
µ
s
SD
ns
rr
Reverse Recovered Charge
Q
= 60A, dI
/dt = 100A/
µ
s
140
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
80
60
40
20
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPER
A
T
URE (
C)
C
C
FIGURE 1.
NORMALIZED POWER DISSI
P
ATION vs CASE
TEMPER
A
TURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE – DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
x Z
x R
+ T
θ
JC C
J
DM
θ
JC
SINGLE PULSE
0.01
-5
-4
-3
10
-2
10
-1
0
1
10
10
10
t, REC
T
A
NGULAR PULSE DURATION (s)
10
10
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
Typical Performance Curves
(Continued)
1000
o
T
= 25
C
FOR TEMPER
A
T
URES
ABOVE 25
C DERATE PEAK
C
o
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
V
= 10V
GS
100
50
TRANSCONDUCTANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
-5
10
-4
10
-3
-2
-1
0
1
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4.
PEAK CURRENT CA
P
A
BILITY
500
If R = 0
500
100
t
= (L)(I
)/(1.3*R
A
T
ED BV
– V
)
AV
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
AS
DSS
DD
T
= MAX RATED
o
J
T
= 25
C
C
t
– V
) +1]
DD
AV
AS
DSS
100
100
µ
s
o
S
T
A
RTING T
= 25
C
J
10
1
1ms
OPERATION IN THIS
AREA M
A
Y
B
E
o
STARTING T
= 150
C
J
LIMITED BY r
10ms
DS(ON)
V
= 55V
DSS(MAX)
10
0.001
0.01
0.1
1
10
1
10
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5.
FORWARD BIAS SAFE OPERATING AREA
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING CA
P
A
BILITY
150
120
90
60
30
0
150
o
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
25 C
V
V
V
= 20V
= 10V
GS
120
90
60
30
0
GS
o
-55 C
= 7V
GS
V
= 6V
GS
o
175 C
V
= 5V
GS
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
V
= 15V
T
= 25
C
DD
C
0
1.5
3.0
4.5
6.0
7.5
0
1.5
3.0
4.5
6.0
7.5
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
V ,
GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 7.
SATURATION CHARACTERISTICS
FIGURE 8.
TRANSFER CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
Typical Performance Curves
(Continued)
1.2
1.0
0.8
0.6
2.5
2.0
1.5
1.0
0.5
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= V
, I
= 250
µ
A
DS D
GS
V
= 10
V
, I
=
6
0A
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPER
A
T
URE (
C)
T ,
JUNCTION TEMPER
A
T
URE (
C)
J
J
FIGURE 9.
NORMALIZED DRAIN TO SOURCE ON
FIGURE 10.
NORMALIZED GATE THRESHOLD VO
L
TAGE vs
JUNCTION TEMPER
A
T
URE
RESIS
T
A
NCE vs JUNCTION TEMPERATURE
2000
1.2
I
= 250
µ
A
V
= 0
V
, f =
1
MHz
D
GS
ISS
C
C
C
= C
+ C
GS
= C
C
GD
RSS
OSS
GD
≈
+ C
1500
1000
500
0
DS
GD
1.1
1.0
0.9
C
ISS
C
C
OSS
RSS
-80
-40
0
40
80
120
160
200
0
10
20
30
40
50
60
o
T ,
JUNCTION TEMPER
A
T
URE (
C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
J
FIGURE 11.
NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12.
CA
P
A
CI
T
A
NCE vs DRAIN TO SOURCE VO
L
TAGE
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
I
= 60A
= 45A
= 30A
= 15A
D
D
D
D
2
V
= 30V
DD
0
0
10
20
30
40
50
60
Q ,
GATE CHARGE (nC)
g
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13.
GATE CHARGE WAVEFORMS FOR CONS
T
A
NT G
A
TE CURRENT
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
–
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 14.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15.
UNCLAMPED ENERGY W
A
VEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
–
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16.
GATE CHARGE TEST CIRCUIT
FIGURE 17.
G
A
TE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18.
SWITCHING TIME TEST CIRCUIT
FIGURE 19.
RESISTIVE SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
PSPICE Electrical Model
.SUBCKT HU
F
A
75332 2 1 3 ;
rev 18 June 2002
CA 12 8
1.8e-9
CB 15 14
1.73e-9
CIN 6 8
1.19e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
–
50
EBREAK 11 7 17
18 58.85
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
+
–
17
18
–
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
16
21
+
–
EVTEMP 20 6 18 22 1
19
MWEAK
LG
A
T
E
EVTEMP
+
8
RGATE
G
A
T
E
1
6
–
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLG
A
T
E
LDRAIN 2 5 1e-9
LGATE 1
9 1e-9
LSOURCE 3 7
1e-9
LSOURCE
CIN
SOURCE
3
7
K1 LSOURCE LGATE 0.0085
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 4.5e-3
RGATE 9 20
1.3
RLDRAIN 2 5 10
RLGATE 1 9 10
RLSOURCE 3 7 10
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
5.95e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
–
S1B
S2B
13
CB
CA
IT
14
+
+
VB
A
T
6
8
5
8
EGS
EDS
+
–
–
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4.6))}
.MODEL DBODYMOD D (IS = 1.3e-12
RS = 3.0e-3
IKF = 20 XTI = 6 TRS1 = 2.7e-3
TRS2 = 7.0e-7
CJO = 1.7e-9
TT = 4.0e-8 M = 0.45 vj = 0.75)
.MODEL DBREAKMOD D (RS = 1.71e-2 IKF = 1.0e-5
TRS1 = -4.0e-4
TRS2 = -1.55e-5)
.MODEL DPLCAPMOD D (CJO = 1.8e-9
IS = 1e-30 N = 1 M = 0.9 vj = 1.45)
.MODEL MMEDMOD NMOS (VTO = 3.183 KP = 2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.3)
.MODEL MSTROMOD NMOS (VTO = 3.66 KP = 51.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3
TC2 = 4.5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.16e-2
TC2 = 1.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.96e-3 TC2 = 2.7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -1.0e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.75e-3
TC2 = 5.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -8
VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -3
VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 0
VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 0.5
VOFF= 0)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatle
y
.
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
SABER Electrical Model
REV 18 June 2002
template hufa75332 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod =
(is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75)
LDRAIN
RLDRAIN
RDBO
D
Y
d..model dbreakmod = ()
DPLCAP
DRAIN
2
5
d..model dplcapmod =
(cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45)
m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1)
sw_vcsp..model s1amod =
(ron = 1e-5, roff = 0.1, von = -8, voff = -3)
sw_vcsp..model s1bmod =
(ron = 1e-5, roff = 0.1, von = -3, voff = -8)
sw_vcsp..model s2amod =
(ron = 1e-5, roff = 0.1, von = 0, voff = 0.5)
sw_vcsp..model s2bmod =
(ron = 1e-5, roff = 0.1, von = 0.5, voff = 0)
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
50
–
c.ca n12 n8 = 1.8e-9
c.cb n15 n14 = 1.73e-9
c.cin n6 n8 = 1.19e-9
71
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
–
19
8
MWEAK
LGATE
EVTEMP
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
DBODY
RGATE
G
A
T
E
1
6
+
–
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
–
RLGATE
i.it n8 n17 = 1
LSOURCE
CIN
SOURCE
3
7
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 1.0e-9
l.lsource n3 n7 = 1.0e-9
RSOURCE
RLSOURCE
k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085
S1A
S2A
RBREAK
12
15
13
14
13
17
18
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
8
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
–
res.rbreak n17 n18
= 1, tc1 = 1.05e-3, tc2 = 4.5e-7
res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7
res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5
res.rdrain n50 n16
= 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5
res.rgate n9 n20 = 1.3
+
+
VB
A
T
6
8
5
8
EGS
EDS
+
–
–
8
22
res.rldrain n2 n5 = 10
RVTHRES
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 10
res.rslc1 n5 n51
= 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 5.95e-3, tc1 = 1e-3, tc2 = 1e-5
res.rvtemp n18 n19
= 1, tc1 = -2.75e-3, tc2 = 5.0e-7
res.rvthres n22 n8
= 1, tc1 = -2.8e-3, tc2 = -1.0e-5
spe.ebreak n11 n7 n17 n18 = 58.85
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6))
}
}
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
SPICE Thermal Model
JUNCTION
th
REV 18June 2002
HUFA75332
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM1 th 6 4.00e-3
CTHERM2 6 5 7.00e-3
CTHERM3 5 4 7.50e-3
CTHERM4 4 3 8.00e-3
CTHERM5 3 2 1.85e-2
CTHERM6 2 tl 12.55
6
RTHERM1 th 6 7.09e-3
RTHERM2 6 5 1.77e-2
RTHERM3 5 4 4.97e-2
RTHERM4 4 3 2.79e-1
RTHERM5 3 2 4.21e-1
RTHERM6 2 tl 5.58e-2
5
SABER Thermal Model
SABER thermal model HUFA75332
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.00e-3
ctherm.ctherm2 6 5 = 7.00e-3
ctherm.ctherm3 5 4 = 7.50e-3
ctherm.ctherm4 4 3 = 8.00e-3
ctherm.ctherm5 3 2 = 1.85e-2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 7.09e-3
rtherm.rtherm2 6 5 = 1.77e-2
rtherm.rtherm3 5 4 = 4.97e-2
rtherm.rtherm4 4 3 = 2.79e-1
rtherm.rtherm5 3 2 = 4.21e-1
rtherm.rtherm6 2 tl = 5.58e-2
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
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Advance Information
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Rev. H7
