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HUFA75645P3, HUFA75645S3S
Data Sheet
December 2001
75A, 100
V
,
0
.014 Ohm, N-Channel,
UltraFET® Power MOSFETs
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
Features
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
• Ultra
Low On-Resistance
– r
DS(ON)
= 0.014
Ω,
V
=
10V
GS
GATE
• Simulation
Models
SOURCE
–
T
e
mperature
Compensated PSPICE® and SABER™
Electrical Models
DRAIN
– Spice
and Saber Thermal Impedance Models
(FLANGE)
HUFA75645P3
HUFA75645S3S
• Peak
Current vs Pulse Width Curve
• UIS
Rating Curve
Symbol
D
S
Ordering Information
PART NUMBER
HUFA75645P3
PACKAGE
TO-220AB
TO-263AB
BRAND
75645P
75645S
G
HUFA75645S3S
NOTE: When
ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA75645S3S
T
.
o
Absolute Maximum Ratings
T
= 25
C, Unless Otherwise Specified
C
HUFA75645P3, HUFA75645S3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
100
100
20
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
o
Continuous (T
= 25
C, V
C
= 10V) (Figure 2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
75
65
A
A
GS
D
D
o
Continuous (T
= 100
C, V
= 10V) (Figure 2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Rating
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25
C .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures 6, 14, 15
310
2.07
W
W/ C
D
o
o
o
Operating and Storage
T
e
mperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T ,
T
J
-55 to 175
C
STG
Maximum
T
e
mperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See
T
e
chbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
o
300
260
C
C
L
pkg
NOTES:
1. T
= 25
C to 150
C.
o
o
J
CAUTION:
Stresses above those listed in “Absol24ute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
o
Electrical Specifications
PARAMETER
T =
25 C,
Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250
µ
A, V
= 0V (Figure 11)
100
–
–
–
–
–
V
DSS
D
GS
GS
GS
I
V
V
V
= 95V, V
= 90V, V
= 0V
–
–
–
1
µ
A
µ
A
nA
DSS
DS
DS
GS
o
= 0V, T
= 150
C
250
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
= 20V
GSS
V
V
= V
, I
= 250
µ
A (Figure 10)
2
–
–
4
V
GS(TH)
GS
DS
D
r
I
= 75A, V
= 10V (Figure 9)
0.0115 0.014
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
R
R
TO-220 and TO-263
–
–
–
–
0.48
62
C/W
θ
JC
o
Thermal Resistance Junction to
Ambient
C/W
θ
JA
SWITCHING SPECIFICATIONS
(V
Turn-On Time
= 10V)
GS
t
t
V
V
R
= 50V, I
= 75A
D
=
10V,
= 2.5
Ω
–
–
–
–
–
–
–
14
117
41
97
–
197
ns
ns
ns
ns
ns
ns
ON
DD
GS
GS
Turn-On Delay Time
Rise Time
–
d(ON)
(Figures 18, 19)
t
–
r
Turn-Off Delay Time
Fall Time
t
–
–
d(OFF)
t
f
Turn-Off Time
t
207
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 50V,
–
–
–
–
–
198
106
6.8
14
238
127
8.2
–
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 75A,
I
I
D
Gate Charge at 10V
Q
g(10)
g(TH)
= 1.0mA
g(REF)
(Figures 13, 16, 17)
Threshold Gate Charge
Q
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
41
–
C
V
= 25V, V
= 0V,
GS
–
–
–
3790
810
–
–
–
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
230
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
145
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
= 75A
= 35A
–
–
–
–
–
–
–
–
SD
SD
SD
SD
SD
V
Reverse Recovery Time
t
= 75A, dI
/dt = 100A/
µ
s
SD
ns
rr
Reverse Recovered Charge
Q
= 75A, dI
/dt = 100A/
µ
s
SD
360
nC
RR
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
20
0
V
= 10V
GS
0
25
50
75
100
150
175
175
25
50
75
100
125
150
125
o
o
T
, CASE TEMPERATURE (
C)
T ,
CASE TEMPER
A
T
URE (
C)
C
C
FIGURE 1.
NORMALIZED POWER DISSI
P
A
T
ION vs CASE
TEMPERATURE
FIGURE 2.
MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE – DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
SINGLE PULSE
PEAK T
= P
x Z
x R
+ T
J
DM
θ
JC
θ
JC C
0.01
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t, REC
T
ANGULAR PULSE DURATION (s)
FIGURE 3.
NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
1000
o
T
= 25
C
C
FOR TEMPERATURES
o
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
V
= 10V
GS
100
50
TRANSCONDUCTANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t, PULSE WIDTH (s)
FIGURE 4.
PEAK CURRENT CA
P
A
BILITY
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
Typical Performance Curves
(Continued)
500
100
600
If R = 0
= (L)(I
)/(1.3*R
A
T
ED BV
t
– V
)
DD
AV
If R
≠
0
AS
DSS
t
AV
= (L/R)ln[(I
*R)/(1.3*R
A
T
ED BV
AS DSS
– V
) +1]
DD
100
100
µ
s
o
S
T
A
RTING T
= 25
C
J
1ms
10
1
OPER
A
T
ION IN THIS
AREA M
A
Y
B
E
o
S
T
A
RTING T
= 150
C
J
LIMITED BY r
DS(ON)
10ms
SINGLE PULSE
T
T
= MAX R
A
T
ED
J
C
o
= 25
C
10
0.001
0.01
0.1
1
1
10
100
300
t
,
T
IME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer
to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6.
UNCLAMPED INDUCTIVE SWITCHING
CA
P
A
BILITY
FIGURE 5.
FORWARD BIAS SAFE OPERATING AREA
150
150
V
= 7V
= 6V
V
= 20V
= 10V
PULSE DURATION = 80
µ
s
GS
GS
V
DUTY CYCLE = 0.5% MAX
V
GS
GS
V
= 15V
DD
120
90
120
90
V
=5V
GS
60
60
o
T
= 175
C
J
o
T
= -55
C
J
PULSE DURATION = 80
µ
s
30
0
30
0
DUTY CYCLE = 0.5% MAX
o
o
T
= 25
C
C
T
= 25
C
J
0
1
2
3
4
2
3
4
5
6
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7.
TRANSFER CHARACTERISTICS
FIGURE 8.
SATURATION CHARACTERISTICS
3.0
1.2
V
= 10
V
, I
=
7
5A
V
= V
, I
= 250
µ
A
DS
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
GS
D
GS
D
2.5
1.0
0.8
2.0
1.5
0.6
0.4
1.0
0.5
-80
-40
0
40
80
120
o
160
200
-80
-40
0
40
80
120
160
200
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
FIGURE 9.
NORMALIZED DRAI
N
T
O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10.
NORMALIZED GAT
E
T
HRESHOL
D
V
OLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
Typical Performance Curves
(Continued)
20000
10000
1.2
V
= 0
V
, f =
1
MHz
I
= 250
µ
A
GS
D
C
=
C
+ C
ISS
GS GD
1.1
1000
C
OSS
≅
C
DS
+ C
GD
1.0
0.9
C
=
C
RSS
GD
100
50
-80
-40
0
40
80
120
160
200
0.1
1.0
10
100
o
T ,
JUNCTION TEMPERATURE (
C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
J
FIGURE 11.
NORMALIZED DRAI
N
T
O SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12.
CA
P
ACITANCE vs DRAIN TO SOURCE VOLTAGE
10
V
= 50V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 75A
= 50A
= 25A
D
D
D
0
30
60
Q ,
GATE CHARGE (nC)
90
120
g
NOTE: Refer
to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13.
GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t
TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
–
V
GS
DUT
t
P
I
AS
0V
0
0.01
Ω
t
AV
FIGURE 14.
UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15.
UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
–
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16.
GATE CHARGE TEST CIRCUIT
FIGURE 17.
GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18.
SWITCHING TIME TEST CIRCUIT
FIGURE 19.
SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
PSPICE Electrical Model
.SUBCKT HUFA75645 2 1 3 ;
rev 21 May 1999
CA 12
8 5.31e-9
CB 15
14 5.31e-9
CIN 6
8 3.56e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17
18 115.5
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
–
50
+
–
17
18
–
DBODY
RDRAIN
6
8
EBREAK
ESG
IT 8 17 1
EVTHRES
+
+
16
21
–
19
8
MWEAK
LDRAIN 2 5 1.0e-9
LGATE 1
9 5.1e-9
LSOURCE 3 7
4.4e-9
LGATE
EVTEMP
+
RGATE
GATE
1
6
–
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.80e-3
RGATE 9 20
0.83
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
1.65e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*205),3.5))}
.MODEL DBODYMOD D (IS = 3.00e-12 IKF = 19
RS = 1.78e-3
XTI = 5 TRS1 = 2.25e-3
TRS2 = 1.00e-5
CJO = 5.32e-9
TT = 7.4e-8 M = 0.68)
.MODEL DBREAKMOD D (RS = 2.15e-1
IKF = 1 TRS1 = 8e-4
TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 5.55e-9
IS = 1e-30
M = 0.98)
.MODEL MMEDMOD NMOS (VTO = 3.13 KP = 10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.83)
.MODEL MSTROMOD NMOS (VTO = 3.51 KP = 93 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.11 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.33 )
.MODEL RBREAKMOD RES (TC1 = 9.9e-4
TC2 = -1.3e-6)
.MODEL RDRAINMOD RES (TC1 = 9.40e-3
TC2 = 2.93e-5)
.MODEL RSLCMOD RES (TC1 = 2.63e-3 TC2 = 1.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.57e-3 TC2 = -7.05e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.87e-3
TC2 = -2.21e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -6.2
VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -2.4
VOFF= -6.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -1.8
VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 0.5
VOFF= -1.8)
.ENDS
NOTE: For
further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatle
y
.
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
SABER Electrical Model
REV 21 May 1999
template ta75645 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod =
(is = 3.00e-12, cjo = 5.32e-9, tt = 7.4e-8, xti = 5, m = 0.68)
d..model dbreakmod = ()
d..model dplcapmod =
(cjo = 5.55e-9, is = 1e-30, vj=1.0, m = 0.8)
m..model mmedmod = (type=_n, vto = 3.13, kp = 10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.51, kp = 93, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.65, kp = 0.11, is = 1e-30, tox = 1)
sw_vcsp..model s1amod =
(ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4)
sw_vcsp..model s1bmod =
(ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2)
sw_vcsp..model s2amod =
(ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod =
(ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 5.31e-9
c.cb n15 n14 = 5.31e-9
c.cin n6 n8 = 3.56e-9
RSLC2
ISCL
50
–
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
8
ESG
EVTHRES
+
+
16
21
–
19
8
MWEAK
i.it n8 n17 = 1
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
–
18
22
EBREAK
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 4.4e-9
MMED
9
20
MSTRO
8
17
18
–
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
7
RSOURCE
RLSOURCE
S1A
S2A
14
res.rbreak n17 n18
= 1, tc1 = 9.9e-4, tc2 = -1.3e-6
res.rdbody n71 n5 = 1.78e-3, tc1 = 2.25e-3, tc2 = 1.e-5
res.rdbreak n72 n5 = 2.15e-1, tc1 = 8e-4, tc2 = 3e-6
res.rdrain n50 n16
= 7.8e-3, tc1 = 9.4e-3, tc2 = 2.93e-5
res.rgate n9 n20 = 0.83
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51
= 1e-6, tc1 = 2.63e-3, tc2 = 1.05e-6
res.rslc2 n5 n50 = 1e3
RBREAK
12
15
13
17
18
8
13
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
res.rsource n8 n7
= 1.65e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19
= 1, tc1 = -2.87e-3, tc2 = -2.21e-6
res.rvthres n22 n8
= 1, tc1 = -2.57e-3, tc2 = -7.05e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 115.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/205))** 3.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
HUFA75645P3, HUFA75645S3S
SPICE Thermal Model
JUNCTION
th
REV 28 July 1999
HUFA75645T
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 8.80e-3
CTHERM2 6 5 2.50e-2
CTHERM3 5 4 2.70e-2
CTHERM4 4 3 3.70e-2
CTHERM5 3 2 4.40e-2
CTHERM6 2 tl 3.40e-1
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 1.20e-2
RTHERM2 6 5 3.00e-2
RTHERM3 5 4 4.30e-2
RTHERM4 4 3 8.80e-2
RTHERM5 3 2 9.90e-2
RTHERM6 2 tl 1.10e-1
5
SABER Thermal Model
SABER thermal model HUFA75645T
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 8.80e-3
ctherm.ctherm2 6 5 = 2.50e-2
ctherm.ctherm3 5 4 = 2.70e-2
ctherm.ctherm4 4 3 = 3.70e-2
ctherm.ctherm5 3 2 = 4.40e-2
ctherm.ctherm6 2 tl = 3.40e-1
rtherm.rtherm1 th 6 = 1.20e-2
rtherm.rtherm2 6 5 = 3.00e-2
rtherm.rtherm3 5 4 = 4.30e-2
rtherm.rtherm4 4 3 = 8.80e-2
rtherm.rtherm5 3 2 = 9.90e-2
rtherm.rtherm6 2 tl = 1.10e-1
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUFA75645P3, HUFA75645S3S Rev. B
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Rev. H4
