onsemi-IRL640A
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December
2013
IRL640A
N-Channel
Logic Level A-FET
200 V,
18
A,
180 m
Ω
Features
Description
•
18
A, 200 V, R
=
180 m
Ω
@ V
=
5
V
DS(on) GS
These N-Channel enhancement mode power field
effect transistors are produced using Fairchild’s
proprietary, planar, DMOS technology. This advanced
technology has been especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices
are well suited for high efficiency switching DC/DC
converters, switch mode power supplies, DC-AC
converters for uninterrupted power supply and motor
control.
•
•
•
•
•
•
Low
G
ate
C
harge (
Typ. 40
nC)
Low Crss (
Typ. 95
pF)
Fast
S
witching
100%
A
valanche
T
ested
Improved dv/dt
C
apability
Logic-Level Gate Drive
D
G
G
D
S
TO-220
S
Absolute Maximum Ratings
Symbol
Characteristic
Value
Units
V
DSS
Drain-to-Source Voltage
V
200
Continuous Drain Current (T
C
=25
°
C)
Continuous Drain Current (T
C
=100
°
C)
Drain Current-Pulsed
18
11.4
63
I
D
A
I
DM
V
GS
E
AS
I
AR
(1)
A
V
Gate-to-Source Voltage
20
±
(2)
(1)
(1)
(3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
64
18
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
C
=25
°
C)
Linear Derating Factor
mJ
V/ns
W
11
5
110
0.88
P
D
T
J
, T
STG
T
L
W/
°
C
Operating Junction and
– 55
to +150
300
Storage Temperature Range
Maximum Lead Temp. for Soldering
°
C
Purposes, 1/8
from case for 5-seconds
Thermal Resistance
Symbol
R
θ
JC
Characteristic
Junction-to-Case
Case-to-Sink
Typ.
Max.
Units
—
0.5
—
1.14
—
R
θ
CS
°
C/W
R
θ
JA
Junction-to-Ambient
62.5
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
1
Package Marking and Ordering Information
Part Number
Top Mark
Package
Packing Method
Reel Size
N/A
Tape Width
Quantity
N/A
50
units
IRL640A
IRL640A
TO-220
Tube
Electrical Characteristics
(T
C
=25
℃
unless otherwise specified)
Symbol
BV
DSS
Characteristic
Min. Typ. Max.
Units
Test Condition
V
GS
=0V,I
D
=250
µ
A
V
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
200 —
—
∆
BV/
∆
T
J
V
GS(th)
I
D
=250
µ
A
See Fig 7
V/
°
C
— 0.17 —
V
DS
=5V,I
D
=250
µ
A
V
GS
=20V
V
1.0
—
—
2.0
100
Gate-Source Leakage
, Forward
Gate-Source Leakage
, Reverse
—
—
—
—
I
GSS
nA
V
GS
=-20V
— -100
V
DS
=200V
—
—
10
I
DSS
Drain-to-Source Leakage Current
µ
A
V
DS
=160V,T
C
=125
°
C
100
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
R
DS(on)
(4)
(4)
V
GS
=5V,I
D
=9A
V
DS
=40V,I
D
=9A
—
—
0.18
Ω
Ω
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
—
—
—
—
—
—
—
—
—
—
—
13.3 —
1310 1705
V
GS
=0V,V
DS
=25V,f =1MHz
See Fig 5
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
250
120
30
25
100
40
56
—
200
95
pF
ns
11
V
DD
=100V,I
D
=18A,
R
G
=4.6
Ω
8
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
46
(4) (5)
See Fig 13
15
Q
g
Total Gate Charge
Gate-Source Charge
Gate-Drain (
Miller ) Charge
V
DS
=160V,V
GS
=5V,
I
D
=18A
40
Q
gs
Q
gd
nC
6.8
18.6
—
See Fig 6 & Fig 12
(4) (5)
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max.
Units
Test Condition
Integral reverse pn-diode
in the MOSFET
—
—
—
—
—
—
—
18
63
1.5
—
A
I
SM
(1)
(4)
V
SD
t
rr
V
—
T
J
=25
°
C,I
S
=18A,V
GS
=0V
T
J
=25
°
C,I
F
=18A
ns
µ
C
224
Q
rr
(4)
1.55 —
di
F
/dt=100A/
µ
s
Notes;
(1) Repetitive
Rating: Pulse Width Limited by Maximum Junction Temperature
(2) L=0.3mH,
I
AS
=18A, V
DD
=50V, R
=27 ,
Starting T
=25 C
Ω
°
G
J
(3) I
SD
18A, di/dt
260A/ s,
V
BV
, Starting T
=25 C
°
DSS J
≤
≤
µ
≤
DD
(4) Pulse
Test: Pulse Width = 250
s, Duty Cycle
2%
µ
≤
(5) Essentially
Independent of Operating Temperature
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
2
ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋ
Fig 1.
Output Characteristics
Fig 2.
Transfer Characteristics
V
GS
Top :
.
0
V
6
.
0
V
5
.
5
V
5
.
0
V
4
.
5
V
4
.
0
V
3
.
5
V
1
10
1
10
150
o
C
Bottom :
3.
0
V
0
10
2
5
o
C
@
N
ote
s
:
1.
G
S
=
0 V
@
N
ote
s
:
2.
D
S
=
4
0 V
3. 25
s Puls
e
T
est
0
10
1. 25
s Puls
e
T
est
–
5
5
o
C
µ
µ
2.
C
=
2
5
o
C
-1
10
-1
0
1
0
2
4
6
8
10
10
10
10
V ,
D
rain-Source Voltage
[V]
V ,
G
ate-Source Voltage
[V]
DS
GS
Fig 3.
On-Resistance vs. Drain Current
Fig 4.
Source-Drain Diode Forward Voltage
0.4
0.3
0.2
0.1
0.0
V
=
5V
1
GS
10
0
10
V
=
1
0
V
@
N
ote
s
:
1.
G
S
=
0 V
GS
15
0
o
C
@
N
ot
e
:T =
2
5
o
C
2
5
o
C
2. 25
µ
s
P
uls
e
T
est
J
-1
0.4
10
0
20
40
60
80
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I ,
D
rain Current [A]
V ,
S
ource-Drain Voltage
[V]
D
SD
Fig 5.
Capacitance vs. Drain-Source Voltage
Fig 6.
Gate Charge vs. Gate-Source Voltage
2000
C
=
C +C (C =
s
horte
d
)
iss gs gd
ds
C
=
C +C
oss ds gd
6
C
i
ss
C
=
C
V
=
4
0
V
1600
1200
800
rss gd
DS
V
=
1
00
V
DS
V
=
1
60
V
DS
4
2
0
C
o
ss
@
N
ote
s
:
1. V
=
0V
GS
2.
f
=1
M
Hz
C
r
ss
400
@
N
ote
s
: I
=
1
8 A
D
0
0
10
1
0
10
20
30
40
10
Q ,
T
otal Gate Charge
[nC]
V ,
D
rain-Source Voltage [V]
G
DS
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
3
(continued)
ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋ
Fig 7.
Breakdown Voltage vs. Temperature
Fig 8.
On-Resistance vs. Temperature
1.2
1.1
1.0
0.9
0.8
2.0
1.5
1.0
0.5
0.0
@
N
ote
s
:
@
N
ote
s
:
1.
GS
=
0 V
1
.
V =5V
GS
2
.
I =9A
D
2.
D
=
2
50
µ
A
-75 -50 -25
0
25
50
75
100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
o
o
T ,
J
unction Temperature
[
C
]
T ,
J
unction Temperature
[
C
]
J
J
Fig 9.
Max. Safe Operating Area
Fig 10.
Max. Drain Current vs. Case Temperature
20
Operation in This Area
i
s
L
imited b
y
R
DS(on)
2
10
15
10
5
100
µ
s
1
m
s
1
10
1
0
m
s
DC
@
N
ote
s
:
1.
C
=
2
5
o
C
0
10
2.
J
=
1
50
o
C
3. S
i
g
le Pulse
-1
0
10
0
1
2
25
50
75
100
125
150
10
10
10
o
T ,
C
ase Temperature
[
C
]
V ,
D
rain-Source Voltage
[V]
c
DS
Fig 11.
Thermal Response
10
0
D=0.5
@ Notes
1. Z
J
C
(t)=1.14
o
C/W Max.
0.2
θ
2. Duty Factor, D=t
1
/t
2
0.1
10
–
1
3. T
J
M
-T
=P
D
M
*Z
J
C
(t)
θ
0.05
P
DM
0.02
0.01
t
1
t
2
single pulse
10
–
2
10
–
5
10
–
4
10
–
3
10
–
2
10
–
1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
4
V
GS
Same Type
as DUT
50K
Ω
Q
g
12V
200nF
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
I
= const.
G
Charge
Figure 12. Gate Charge Test Circuit & Waveform
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
V
GS
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Figure 13. Resistive Switching Test Circuit & Waveforms
BV
DSS
——————–
BV
DSS
– V
DD
L
1
2
2
—-
E
AS
=
L I
AS
V
DS
I
D
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
V
DS
(t)
V
DD
DUT
G
S
t
p
t
p
Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
5
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
6
Mechanical Dimensions
Figure
16
. TO220, Molded, 3-Lead, Jedec Variation AB
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
7
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
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intended to be an exhaustive list of all such trademarks.
AccuPower™
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BitSiC™
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Sync-Lock™
®*
®
®
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tm
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SM
GreenBridge™
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QS™
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®
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®
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max
™
GTO™
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Definition of Terms
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Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
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Not In Production
Rev. I66
8
©1999 Fairchild Semiconductor Corporation
IRL640A
Rev. C0
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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1050
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone
: 303
−
675
−
2175 or 800
−
344
−
3860
T
o
ll Free USA/Canada
Fax
: 303
−
675
−
2176 or 800
−
344
−
3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
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Semiconductor Components Industries, LLC
