onsemi-IRLR130ATM
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IRLR/U130A
FEATURES
BV
DSS
= 100
V
R
DS(on)
= 0.12
Ω
I
D
= 13
A
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
♦
♦
♦
♦
♦
♦
♦
Improved Gate Charge
Extended Safe Operating Area
D-PAK
I-PAK
Lower Leakage Current:
10 A
(Max.) @ V
DS
= 100V
µ
Lower R
DS(ON)
: 0.101
(Typ.)
2
Ω
1
1
2
3
3
1. Gate
2. Drain
3. Source
Absolute Maximum Ratings
Symbol
Characteristic
Value
100
13
Units
V
DSS
Drain-to-Source Voltage
V
Continuous Drain Current (T
C
=25
°
C)
Continuous Drain Current (T
C
=100
°
C)
Drain Current-Pulsed
I
D
A
8
I
DM
V
GS
E
AS
I
AR
(1)
45
A
V
Gate-to-Source Voltage
20
±
(2)
(1)
(1)
(3)
Single Pulsed Avalanche Energy
Avalanche Current
225
13
mJ
A
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
4.6
6.5
2.5
46
mJ
V/ns
W
*
Total Power Dissipation (T
A
=25
°
C)
Total Power Dissipation (T
C
=25
°
C)
Linear Derating Factor
P
D
W
0.37
W/
°
C
Operating Junction and
T
J
, T
STG
– 55
to +150
300
Storage Temperature Range
°
C
Maximum Lead Temp. for Soldering
Purposes, 1/8
from case for 5-seconds
T
L
Thermal Resistance
Symbol
R
θ
JC
Characteristic
Typ.
Max.
Units
Junction-to-Case
—
—
—
2.7
50
R
θ
JA
*
Junction-to-Ambient
Junction-to-Ambient
°
C/W
R
θ
JA
110
When mounted on the minimum pad size recommended
(PCB Mount).
*
Rev. B
©1999 Fairchild Semiconductor Corporation
1
IRLR/U130A
Electrical Characteristics
(T
C
=25
°
C unless
otherwise specified)
Symbol
BV
DSS
Characteristic
Min. Typ. Max.
Units
Test Condition
V
GS
=0V,I
D
=250
µ
A
V
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
100 —
—
—
∆
BV/
∆
T
J
V
GS(th)
I
D
=250
µ
A
See Fig 7
V/
°
C
—
1.0
—
0.1
V
DS
=5V,I
D
=250
µ
A
V
GS
=20V
V
—
—
2.0
100
Gate-Source Leakage
, Forward
Gate-Source Leakage
, Reverse
I
GSS
nA
V
GS
=-20V
—
— -100
V
DS
=100V
—
—
—
10
I
DSS
Drain-to-Source Leakage Current
µ
A
V
DS
=80V,T
C
=150
°
C
—
100
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
R
DS(on)
(4)
(4)
V
GS
=5V,I
D
=6.5A
V
DS
=40V,I
D
=6.5A
—
—
0.12
Ω
Ω
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
—
—
—
—
—
—
—
—
—
—
—
10.1 —
580 755
V
GS
=0V,V
DS
=25V,f =1MHz
See Fig 5
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
175
75
30
30
70
40
24
—
140
60
pF
ns
10
V
DD
=50V,I
D
=14A,
R
G
=6
Ω
11
t
d(off)
t
f
Turn-Off Delay Time
Fall Time
29
(4) (5)
See Fig 13
15
Q
g
Total Gate Charge
Gate-Source Charge
Gate-Drain (
Miller ) Charge
V
DS
=80V,V
GS
=5V,
I
D
=14A
16.9
2.7
9.7
Q
gs
Q
gd
nC
—
See Fig 6 & Fig 12
(4) (5)
Source-Drain Diode Ratings and Characteristics
Symbol
I
S
Characteristic
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min. Typ. Max.
Units
Test Condition
Integral reverse pn-diode
in the MOSFET
—
—
—
—
—
—
—
13
45
1.5
—
A
I
SM
(1)
(4)
V
SD
t
rr
V
—
T
J
=25
°
C,I
S
=13A,V
GS
=0V
T
J
=25
°
C,I
F
=14A
ns
µ
C
109
Q
rr
(4)
0.41 —
di
F
/dt=100A/
µ
s
Notes;
(1) Repetitive
Rating: Pulse Width Limited by Maximum Junction Temperature
(2) L=2mH,
I
AS
=13A, V
DD
=25V, R
=27 ,
Starting T =25 C
Ω
°
G
J
(3) I
SD
14A, di/dt
350A/ s,
V
BV
, Starting T
=25 C
°
DSS J
≤
≤
µ
≤
DD
(4) Pulse
Test: Pulse Width = 250
s, Duty Cycle
2%
µ
≤
(5) Essentially
Independent of Operating Temperature
2
IRLR/U130A
Fig 1.
Output Characteristics
Fig 2.
Transfer Characteristics
2
10
V
GS
T
o
p :
7
.
0V
6
.
0
V
5
.
5
V
5
.
0
V
4
.
5
V
4
.
0
V
3
.
5
V
1
10
1
10
Bo
t
t
o
m :
3
.
0V
15
0
o
C
0
10
2
5
o
C
@
N
ote
s
:
1. V
G
S
=
0 V
2. V
D
S
=
4
0 V
@
N
ote
s
:
0
–
5
5
o
C
10
1. 250
s
P
uls
e
T
est
µ
3. 250
s Puls
e
T
est
µ
2. T
=
2
5
o
C
C
-1
10
-1
0
1
0
2
4
6
8
10
10
10
10
V
D
S
,
D
rain-Source Voltage
[V]
V
G
S
,
G
ate-Source Voltage
[V]
Fig 3.
On-Resistance vs. Drain Current
Fig 4.
Source-Drain Diode Forward Voltage
0.20
V
GS
=
5V
0.15
0.10
0.05
0.00
1
10
0
10
V
GS
=
1
0
V
@
N
ote
s
:
1. V
G
S
=
0 V
2. 25
0
µ
s
P
uls
e
T
est
15
0
o
C
@
N
ot
e
:T =
2
5
o
C
2
5
o
C
J
-1
10
0
15
30
45
60
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
I ,
D
rain Current [A]
V
S
D
,
S
ource-Drain Voltage
[V]
D
Fig 5.
Capacitance vs. Drain-Source Voltage
Fig 6.
Gate Charge vs. Gate-Source Voltage
1000
800
600
400
200
C
iss
=
C +
C
g
d
(C =
s
horte
d
)
gs ds
C
oss
=
C +C
ds gd
6
C
i
ss
V
DS
=
2
0 V
DS
=
5
0 V
DS
=
8
0 V
C
r
ss
=
C
gd
V
V
4
2
0
C
o
ss
@
N
ote
s
:
1. V
G
S
=
0V
2.
f
=1
M
Hz
C
r
ss
@
N
ote
s
: I
=
1
4 A
D
0
0
10
1
0
3
6
9
12
15
18
10
Q ,
T
otal Gate Charge
[nC]
V
DS
,
D
rain-Source Voltage [V]
G
IRLR/U130A
Fig 7.
Breakdown Voltage vs. Temperature
Fig 8.
On-Resistance vs. Temperature
1.2
2.5
2.0
1.5
1.0
0.5
0.0
1.1
1.0
@
N
ote
s
:
0.9
0.8
@
N
ote
s
:
1. V
=
5V
1. V
=
0 V
GS
GS
2. I
=
7A
2. I
=
2
50
A
µ
D
D
-75 -50 -25
0
25
50
75
100 125 150 175
-75 -50 -25
0
25
50
75
100 125 150 175
o
o
T ,
J
unction Temperature
[
C
]
T ,
J
unction Temperature
[
C
]
J
J
Fig 9.
Max. Safe Operating Area
Fig 10.
Max. Drain Current vs. Case Temperature
15
Operation in This Area
i
s
L
imited b
y
R
D
S(on)
2
10
12
9
10
0
µ
s
1
m
s
1
10
1
0
m
s
DC
6
@
N
ote
s
:
1. T
=
2
5
o
C
0
C
10
2. T
=
1
5
0
o
C
J
3
3. Single Pulse
-1
0
10
0
1
2
25
50
75
100
125
150
10
10
10
o
T ,
C
ase Temperature
[
C
]
V
D
S
,
D
rain-Source Voltage
[V]
c
Fig 11.
Thermal Response
D=0.5
0.2
10
0
10
–
1
10
–
2
@ Notes :
1. Z
J
C
(t)=2.7
o
C/W Max.
θ
0.1
2. Duty Factor, D=t
1
/t
2
0.05
0.02
0.01
3. T
J
M
-T
C
=P
D
M
*Z (t)
θ
J
C
P
DM
single pulse
t
1
t
2
10
–
5
10
–
4
10
–
3
10
–
2
10
–
1
10
0
10
1
t
1
, Square Wave Pulse Duration
[sec]
IRLR/U130A
Fig 12.
Gate Charge Test Circuit
& Waveform
Current Regulator
V
GS
Same Type
as DUT
50k
Ω
Q
g
200nF
12V
10V
300nF
V
DS
Q
gs
Q
gd
V
GS
DUT
R
2
3mA
R
1
Charge
Current Sampling (I
G
) Current
Sampling (I
D
)
Resistor Resistor
Fig 13.
Resistive Switching Test Circuit
& Waveforms
R
L
V
out
V
in
V
out
90%
V
DD
( 0.5 rated V
DS
)
R
G
DUT
10%
V
in
5V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Fig 14.
Unclamped Inductive Switching Test Circuit
& Waveforms
BV
DSS
1
2
2
L
L
I
D
—-
——————–
E
AS
=
L
L
I
AS
BV
DSS
— V
DD
V
DS
BV
DSS
I
AS
Vary t
p
to obtain
required peak I
D
R
G
I
D
(t)
V
DD
C
DUT
V
DS
(t)
V
DD
5V
t
p
t
p
Time
5
IRLR/U130A
Fig 15.
Peak Diode Recovery dv/dt Test Circuit
& Waveforms
+
DUT
V
DS
—
I
S
L
Driver
V
GS
Same Type
as DUT
R
G
V
DD
V
GS
dv/dt controlled by
R
G
I
S
controlled by Duty Factor
D
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
5V
( Driver )
I
FM
, Body Diode Forward Current
I
S
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
6
DPAK Package
Dimensions
D
– PAK
Dimensions in Millimeters
September 1999, Rev B
IPAK Package
Dimensions
I
– PAK
Dimensions in Millimeters
September 1999, Rev B
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Y
,
F
UNCTION OR DESIGN. FAIRCHILD
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OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. E
