onsemi-ISL9N308AD3
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June 2002
PWM Optimized
ISL9N308AD3 / ISL9N308AD3ST
®
N-Channel Logic Level UltraFET
Trench Power MOSFETs
30V, 50A, 8m
Ω
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
•
•
•
•
•
•
Fast switching
r
r
= 0.0064
Ω
(Typ), V
= 10V
GS
DS(ON)
DS(ON)
= 0.010
Ω
(Typ), V
= 4.5V
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
GS
Q (Typ)
= 24nC, V
= 5V
g
GS
Q
(Typ) = 8nC
gd
ISS
Applications
•
DC/DC converters
C
(Typ) = 2600pF
D
S
D
G
S
G
I-PAK
(TO-251AA)
D-PAK
(TO-252)
G D S
MOSFET Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
Parameter
Ratings
30
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
±
20
Drain Current
o
50
48
A
A
Continuous (T
= 25 C, V
= 10V) Note 1
C
GS
o
I
Continuous (T
= 100 C, V
= 4.5V) Note 1
C GS
D
o
o
Continuous (T
= 25 C, V
= 10V, R
= 52 C/W)
θ
JC
14
A
C
GS
Pulsed
Figure 4
A
Power dissipation
Derate above 25 C
100
0.67
W
W/ C
P
o
o
D
o
T , T
Operating and Storage
T
e
mperature
-55 to 175
C
J
STG
Thermal Characteristics
o
o
o
R
R
R
Thermal Resistance Junction to Case TO-252, TO-251
Thermal Resistance Junction to Ambient TO-252, TO-251
1.5
100
52
C/W
C/W
C/W
θ
JC
θ
JA
θ
JA
2
Thermal Resistance Junction to Ambient TO-252, 1in
copper pad area
Package Marking and Ordering Information
Device Marking
N308AD
Device
Package
TO-252AA
TO-251AA
Reel Size
330mm
T
u
be
Tape Width
Quantity
2500 units
75 units
ISL9N308AD3ST
ISL9N308AD3
16mm
N/A
N308AD
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Electrical Characteristics
T =
25
°
C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250
µ
A, V
= 0V
30
–
–
–
–
–
–
V
VDSS
D
GS
V
V
V
= 25V
= 0V
1
DS
GS
GS
I
I
µ
A
nA
DSS
o
T
= 150
–
250
±
100
C
=
±
20V
–
GSS
On Characteristics
V
Gate to Source Threshold Voltage
V
= V
, I
= 250
µ
A
1
–
–
3
V
GS(TH)
GS
DS
D
I
I
= 50A, V
= 10V
0.0064 0.008
D
D
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 48A, V
= 4.5V
–
0.010
0.012
GS
Dynamic Characteristics
C
C
C
Input Capacitance
–
–
–
–
–
–
–
–
2600
520
225
45
–
–
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 15V, V
= 0V,
GS
DS
Output Capacitance
OSS
RSS
f = 1MHz
Reverse
T
r
ansfer Capacitance
T
o
tal Gate Charge at 10V
T
o
tal Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain
“
Miller
”
Charge
–
Q
Q
Q
Q
Q
V
V
V
= 0V to 10V
= 0V to
5V
= 0V to 1V
68
37
4.0
–
g(TOT)
g(5)
g(TH)
gs
GS
GS
GS
24
V
= 15V
DD
= 48A
I
2.6
7
D
I =
1.0mA
g
8
–
gd
Switching Characteristics
(V =
4.5V)
GS
t
t
t
t
t
t
T
u
rn-On Time
T
u
rn-On Delay Time
Rise Time
–
–
–
–
–
–
–
122
ns
ns
ns
ns
ns
ns
ON
15
67
35
32
–
–
d(ON)
–
V
V
= 15
V
, I
=
1
4A
r
DD
GS
D
= 4.5V, R
= 6.2
Ω
T
u
rn-Off Delay Time
Fall Time
–
–
GS
d(OFF)
f
T
u
rn-Off Time
100
OFF
Switching Characteristics
(V =
10V)
GS
t
t
t
t
t
t
T
u
rn-On Time
T
u
rn-On Delay Time
Rise Time
–
–
–
–
–
–
–
71
ns
ns
ns
ns
ns
ns
ON
8
–
d(ON)
40
64
31
–
–
V
V
= 15
V
, I
=
1
4A
r
DD
GS
D
= 10V, R
= 6.2
Ω
T
u
rn-Off Delay Time
Fall Time
–
–
GS
d(OFF)
f
T
u
rn-Off Time
142
OFF
Unclamped Inductive Switching
t
Avalanche Time
I
= 3.2A, L = 3.0mH
215
–
–
µ
s
AV
D
Drain-Source Diode Characteristics
I
I
I
I
= 48A
= 20A
–
–
–
–
–
–
–
–
1.25
1.0
26
V
V
SD
SD
SD
SD
V
Source to Drain Diode Voltage
SD
t
Reverse Recovery Time
= 48A, dI
/dt = 100A/
µ
s
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 48A, dI
/dt = 100A/
µ
s
14
RR
SD
Notes:
1:
TO-251AA continuous current limited by package to 35A.
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Typical Characteristic
T =
25
°
C unless otherwise noted
C
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
V
= 10V
GS
V
= 4.5V
GS
0
25
50
75
100
150
175
125
o
25
50
75
T ,
CASE TEMPER
A
T
URE (
C)
C
100
125
150
175
o
T
, CASE TEMPERATURE (
C)
C
Figure 1.
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
NOTES:
DUTY
F
ACTOR: D = t
/t
1
2
PEAK T
= P
x Z
x R
+ T
θ
JC C
J
DM
θ
JC
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, REC
T
ANGULAR PULSE DURATION (s)
10
10
10
Figure 3.
Normalized Maximum Transient Thermal Impedance
1000
o
T
= 25
C
C
FOR TEMPERATURES
o
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
V
= 10V
GS
V
= 5V
GS
100
40
TRANSCONDUCTANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4.
Peak Current Capability
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Typical Characteristic
(Continued) T
= 25
°
C unless otherwise noted
C
100
75
50
25
0
100
75
50
25
0
PULSE DURATION = 80
µ
s
V
= 10V
GS
DUTY CYCLE = 0.5% MAX
V
= 4.5V
GS
V
= 15V
DD
V
= 3.5V
GS
o
T
= 175
C
J
V
= 3V
GS
o
o
T =
-55 C
J
T
= 25
C
J
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
T
= 25
C
C
0
0.5
1.0
1.5
2.0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 5.
Transfer Characteristics
Figure 6.
Saturation Characteristics
25
20
15
10
5
2.0
PULSE DUR
A
T
ION = 80
µ
s
PULSE DUR
A
T
ION = 80
µ
s
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
o
I
= 32A
T
= 25
C
D
C
1.5
I
= 50A
I
= 14A
D
D
1.0
0.5
V
= 10
V
, I
=
5
0A
D
GS
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, G
A
T
E TO SOURCE VOLTAGE (V)
T ,
JUNCTION TEMPERATURE (
C)
GS
J
Figure 7.
Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8.
Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
1.4
I =
250
µ
A
D
V
= V
, I
= 250
µ
A
GS
DS
D
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T ,
JUNCTION TEMPER
A
T
URE (
C)
T , JUNCTION TEMPER
A
T
URE (
C)
J
J
Figure 9.
Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10.
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Typical Characteristic
(Continued) T
= 25
°
C unless otherwise noted
C
4000
10
V
= 15V
DD
C
=
C +
C
GD
ISS
GS
8
C
C
+ C
OSS
DS GD
1000
6
C
=
C
GD
RSS
4
WAVEFORMS IN
DESCENDING ORDER:
2
I
I
= 48A
= 14A
D
D
V
= 0
V
, f =
1
MHz
GS
0
100
30
0.1
1
10
0
10
20
30
40
50
V
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
DS
g
Figure 11.
Capacitance vs Drain to Source
Voltage
Figure 12.
Gate Charge Waveforms for Constant
Gate Currents
250
350
V
= 10
V
, V
=
1
5
V
, I
=
1
4A
GS
DD
D
V
= 4.5
V
, V
=
1
5
V
, I
=
1
4A
DD D
GS
300
250
200
150
100
50
200
150
100
50
t
r
t
d(OFF)
t
d(OFF)
t
f
t
f
t
d(ON)
t
r
t
d(ON)
0
0
0
10
20
30
40
50
0
10
20
30
40
50
R
, G
A
T
E TO SOURCE RESISTANCE (
Ω
)
R
, G
A
T
E TO SOURCE RESISTANCE (
Ω
)
GS
GS
Figure 13.
Switching Time vs Gate Resistance
Figure 14.
Switching Time vs Gate Resistance
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t
TO OBTAIN
P
+
–
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01
Ω
t
AV
Figure 15.
Unclamped Energy Test Circuit
Figure 16.
Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Test Circuits and Waveforms
(Continued)
V
DS
V
Q
g(TOT)
DD
R
L
V
DS
V
= 10V
GS
Q
g(5)
V
GS
+
–
V
V
= 5V
DD
V
GS
GS
V
= 1V
DUT
GS
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17.
Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
–
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19.
Switching Time Test Circuit
Figure 20.
Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
, and the
thermal resistance of the heat dissipating path determines
125
100
75
JM
R
= 33.32 + 23.84/(0.268+Area)
θ
JA
the maximum allowable device power dissipation, P
, in an
DM
application.
Therefore the application
’
s ambient
o
o
temperature, T
( C), and thermal resistance R
( C/W)
A
θ
JA
must be reviewed to ensure that T
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(
T
–
T
)
JM
Z
A
(EQ. 1)
P
=
–
—————————-
DM
50
θ
JA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part
’
s current and maximum
25
0.01
0.1
1
2
10
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
AREA, TOP COPPER AREA (in
)
DM
Figure 21.
Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer
’
s preliminary application evaluation. Figure 21
defines the R
for the device as a function of the top
θ
JA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are R
values listed in the
θ
JA
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
.
DM
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
is defined as the natural log of the area
θ
JA
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
23.84
(
0.268 +
Area
)
R
=
33.32 +
–
———————————
–
–
(EQ. 2)
θ
JA
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
PSPICE Electrical Model
.SUBCKT ISL9N308AD3ST 2 1 3 ;
rev Dec2000
CA 12 8
1.5e-9
CB 15 14
1.75e-9
CIN 6 8
2.35e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
DBODY 7 5 DBODYMOD
DBREAK 5 11
DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
EBREAK 11 7 17
18 32.7
EDS 14 8 5 8
1
EGS 13 8 6 8
1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8
1
EVTEMP 20 6 18 22 1
11
–
50
+
–
17
18
–
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
16
21
+
–
19
8
MWEAK
LG
A
T
E
EVTEMP
IT 8 17 1
RG
A
T
E
GATE
1
+
6
–
18
22
MMED
9
20
LDRAIN 2 5 1e-9
LGATE 1
9 4.58e-9
LSOURCE 3 7
1.47e-9
MSTRO
8
RLG
A
T
E
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.5e-3
RGATE 9 20
3.4
RLDRAIN 2 5 10
RLGATE 1 9 45.8
RLSOURCE 3 7 14.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD
2.55e-3
RVTHRES 22 8 RVTHRESMOD
1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19
DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),5))}
.MODEL DBODYMOD D (IS = 1.9e-11 N = 1.075
RS = 4.2e-3
TRS1 = 9e-4
TRS2 = 1e-6 XTI = 2.2
CJO = 1.1e-9
TT =
8e-11
M = 0.49)
.MODEL DBREAKMOD D (RS = 1.7e-1
TRS1 = 1e-3
TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 8.2e-10
IS = 1e-30
N = 10 M = 0.45)
.MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.4)
.MODEL MSTROMOD NMOS (VTO = 2.35KP = 90 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 34 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3
TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 7e-3
TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.7e-3 TC2 = -1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.8e-3
TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -4.0
VOFF= -0.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -0.8
VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = -0.3
VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
VON = 0.2
VOFF= -0.3)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
SABER Electrical Model
REV Dec 2000
template ISL9N308AD3ST n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod =
(isl = 1.9e-11, nl=1.075 , rs = 4.2e-3, trs1 = 9e-4, trs2 = 1e-6, xti=2.2, cjo = 1.1e-9, tt = 8e-11, m = 0.49,)
dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod =
(cjo = 8.2e-10, isl=10e-30, nl=10, m=0.45)
m..model mmedmod = (type=_n, vto = 1.9, kp=3, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.35, kp = 90, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod =
(ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8)
sw_vcsp..model s1bmod =
(ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0)
sw_vcsp..model s2amod =
(ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
sw_vcsp..model s2bmod =
(ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)
LDRAIN
DPLCAP
5
DRAIN
2
10
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.75e-9
c.cin n6 n8 = 2.35e-9
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
DBREAK
11
50
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
–
RDRAIN
6
ESG
8
DBODY
EVTHRES
+
16
21
i.it n8 n17 = 1
+
–
19
8
MWEAK
LG
A
T
E
EVTEMP
RG
A
T
E
G
A
T
E
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.58e-9
l.lsource n3 n7 = 1.47e-9
+
6
–
18
22
EBREAK
+
MMED
9
20
MSTRO
17
18
–
RLGATE
LSOURCE
CIN
SOURCE
3
8
7
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
S1A
12
S2A
RBREAK
15
13
8
14
13
res.rbreak n17 n18
= 1, tc1 = 1e-3, tc2 = -7e-7
res.rdrain n50 n16
= 2.5e-3, tc1 = 7e-3, tc2 = 1e-5
res.rgate n9 n20 = 3.4
17
18
RVTEMP
19
S1B
S2B
13
CB
res.rldrain n2 n5 = 10
CA
IT
14
–
+
+
res.rlgate n1 n9 = 45.8
res.rlsource n3 n7 = 14.7
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
RVTHRES
res.rsource n8 n7
= 2.55e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19
= 1, tc1 = -1.8e-3, tc2 = 1e-6
res.rvthres n22 n8
= 1, tc1 = -2.7e-3, tc2 = -1e-5
spe.ebreak n11 n7 n17 n18 = 32.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/200))** 5))
}
}
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
SPICE Thermal Model
JUNCTION
th
REV 23 Sept 2000
ISL9N308AT
CTHERM1 th 6 2.0e-4
CTHERM2 6 5 3.0e-3
CTHERM3 5 4 3.4e-3
CTHERM4 4 3 4.0e-3
CTHERM5 3 2 1.0e-2
CTHERM6 2 tl 5.0e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 th 6 1.5e-3
RTHERM2 6 5 5.5e-3
RTHERM3 5 4 5.2e-2
RTHERM4 4 3 3.5e-1
RTHERM5 3 2 3.8e-1
RTHERM6 2 tl 4.1e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model ISL9N308AT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.0e-4
ctherm.ctherm2 6 5 = 3.0e-3
ctherm.ctherm3 5 4 = 3.4e-3
ctherm.ctherm4 4 3 = 4.0e-3
ctherm.ctherm5 3 2 = 1.0e-2
ctherm.ctherm6 2 tl = 5.0e-2
4
3
2
rtherm.rtherm1 th 6 = 1.5e-3
rtherm.rtherm2 6 5 = 5.5e-3
rtherm.rtherm3 5 4 = 5.2e-2
rtherm.rtherm4 4 3 = 3.5e-1
rtherm.rtherm5 3 2 = 3.8e-1
rtherm.rtherm6 2 tl = 4.1e-1
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
ISL9N308AD3 / ISL9N308AD3ST Rev C
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
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Preliminary
First Production
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Rev. H7
