onsemi-MAC15M

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onsemi-MAC15M
MAC15M, MAC15N  
Triacs  
Silicon Bidirectional Thyristors  
Designed for high performance full-wave AC control applications  
where high noise immunity and high commutating di/dt are required.  
Features  
•
Blocking
V
o
ltage to 800
V
o
lts  
TRIACS  
•
On-State Current Rating of 15 Amperes RMS at 80
°
C  
•
Uniform Gate Trigger Currents in Three Modes  
•
High Immunity to dv/dt − 250 V/
m
s minimum at 125
°
C  
•
Minimizes Snubber Networks for Protection  
•
Industry Standard TO−220 Package  
15 AMPERES RMS  
600 thru 800 VOLTS  
MT2  
MT1  
G
•
High Commutating di/dt − 9.0 A/ms minimum at 125
°
C  
•
Operational in Three Quadrants, Q1, Q2, and Q3  
•
These Devices are Pb−Free and are RoHS Compliant*  
MARKING  
DIAGRAM  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
MAC15xG  
AYWW  
Peak Repetitive Off−State Voltage (Note 1)  
V
V
V
DRM,  
RRM  
(
−
4
0 to 125
°
C, Sine Wave, 50 to 60 Hz,  
Gate Open)  
MAC15M  
MAC15N  
600  
800  
TO−220  
CASE 221A  
STYLE 4  
1
2
3
On−State RMS Current  
I
15  
A
A
T(RMS)  
(Full Cycle Sine Wave, 60 Hz, T
 
= 80
°
C)  
C
x
A
Y
= M or N  
Peak Non-repetitive Surge Current  
(One Full Cycle Sine Wave, 60 Hz,  
T =
 
125
°
C)  
J
I
150  
TSM  
= Assembly Location  
=
Y
e
ar  
WW =
 
Work Week  
2
2
Circuit Fusing Consideration (t = 8.3 ms)  
I t  
93  
20  
A s  
G
= Pb−Free Package  
Peak Gate Power  
P
W
W
GM  
(Pulse Width
≤
1.0
m
s, T
 
= 80
°
C)  
C
PIN ASSIGNMENT  
Main
T
e
rminal 1  
Main
T
e
rminal 2  
Gate  
Average Gate Power  
P
0.5  
G(AV)  
1
(t = 8.3 ms, T
 
= 80
°
C)  
C
2
3
4
Operating Junction
T
e
mperature Range  
Storage
T
e
mperature Range  
T
J
−40 to +125  
−40 to +150  
°
C  
°
C  
T
stg  
Main
T
e
rminal 2  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. V  
and V  
for all types can be applied on a continuous basis. Blocking  
DRM  
RRM  
ORDERING INFORMATION  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
Device  
Package  
Shipping  
MAC15MG  
TO−220  
50 Units / Rail  
(Pb−Free)  
MAC15NG  
TO−220  
50 Units / Rail  
(Pb−Free)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting
T
e
chniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
November, 2014 − Rev. 3  
MAC15M/D  

MAC15M, MAC15N  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Value  
Unit  
Thermal Resistance,
 
Junction−to−Case  
Thermal Resistanc
e
Junction−to−Ambient  
R
R
2.0  
62.5  
°
C/W  
q
q
JC  
JA  
Maximum Lead
T
e
mperature for Soldering Purposes 1/8
″
from Case for 10 Seconds  
T
L
260  
°
C  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted; Electricals apply in both directions)  
J
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Peak Repetitive Blocking Current  
I
,
mA  
DRM  
(V =
 
Rated V  
, V  
RRM  
; Gate Open)  
T =
 
25
°
C  
T =
 
125
°
C  
J
I
RRM  
−
−
−
−
0.01  
2.0  
D
DRM  
J
ON CHARACTERISTICS  
Peak On-State Voltage (Note 2)  
(I 21
 
A Peak)  
Gate Trigger Current (Continuous DC) (V
 
= 12
V
, R
 
=
1
00
W
)  
V
V
TM  
=
−
1.2  
1.6  
TM  
I
mA  
D
L
GT  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
5.0  
5.0  
5.0  
13  
16  
18  
35  
35  
35  
Hold Current  
I
mA  
mA  
H
(V =
 
12 Vdc, Gate Open, Initiating Current =
 
150 mA)  
D
−
20  
40  
Latching Current (V
 
= 24
V
, I
 
=
3
5 mA)  
I
D
G
L
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
−
−
−
33  
36  
33  
50  
80  
50  
Gate Trigger Voltage (V
 
= 12 V, R
 
= 100
W
)  
V
GT  
V
D
L
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
0.5  
0.5  
0.5  
0.75  
0.72  
0.82  
1.5  
1.5  
1.5  
DYNAMIC CHARACTERISTICS  
Rate of Change of Commutating Current; See Figure 10.  
(V =
 
400
V
, I
 
=
6
.0 A, Commutating dv/dt = 24 V/
m
s,  
(di/dt)  
9.0  
−
−
−
−
A/ms  
c
C =
 
10
m
F  
L =
 
40 mH  
L
D
TM  
L
Gate Open, T
 
= 125
°
C, f = 250 Hz, No Snubber)  
J
Critical Rate of Rise of Off-State Voltage  
dv/dt  
250  
V/
m
s  
(V =
 
Rated V  
, Exponential Waveform, Gate Open, T
 
= 125
°
C)  
J
D
DRM  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
2. Pulse
 
T
e
st: Pulse Width
≤
2.0 ms, Duty Cycle
≤
2%.  
2

MAC15M, MAC15N  
Voltage Current Characteristic of Triacs  
(Bidirectional Device)  
+ Current  
Quadrant 1  
Main
T
e
rminal 2 +  
Symbol  
Parameter  
V
TM  
V
Peak Repetitive Forward Off State Voltage  
Peak Forward Blocking Current  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
V
Peak Repetitive Reverse Off State Voltage  
Peak Reverse Blocking Current  
RRM  
RRM  
RRM  
I
V
Maximum On State Voltage  
Holding Current  
+ Voltage  
off state  
TM  
I
H
I
at V  
DRM  
DRM  
I
H
Quadrant 3  
Main
T
e
rminal 2 −  
V
TM  
Quadrant Definitions for a Triac  
MT2 POSITIVE  
(Positive Half Cycle)  
+
(+) MT2  
(+) MT2  
Quadrant II  
Quadrant I  
(−) I  
(+) I  
GT  
GT  
GATE  
GATE  
MT1  
MT1  
REF  
REF  
I
−
+ I  
GT  
GT  
(−) MT2  
(−) MT2  
Quadrant III  
Quadrant IV  
(+) I  
(−) I  
GT  
GT  
GATE  
GATE  
MT1  
REF  
MT1  
REF  
−
MT2 NEGATIVE  
(Negative Half Cycle)  
All polarities are referenced to MT1.  
With in−phase signals (using standard AC lines) quadrants I and III are used.  
3

MAC15M, MAC15N  
125  
120  
115  
110  
105  
100  
95  
20  
18  
16  
DC  
180
°  
120
°  
90
°  
α
= 30 and 60
°  
14  
12  
10  
8
60
°  
α
= 90
°  
α
= 180
°  
α
= 120
°  
α
= 30
°  
6
DC  
90  
4
85  
2
80  
0
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
I
, RMS ON‐STATE CURRENT (AMP)  
I
T(RMS)  
, ON‐STATE CURRENT (AMP)  
T(RMS)  
Figure 1. RMS Current Derating  
Figure 2. On−State Power Dissipation  
100  
10  
1
1
TYPICAL AT  
T =
 
25
°
C  
MAXIMUM @ T
 
= 125
°
C  
J
J
0.1  
0.01  
4
0.1  
1
10  
100  
t, TIME (ms)  
1000  
1ꢀ·ꢀ10  
Figure 4. Transient Thermal Response  
MAXIMUM @ T
 
= 25
°
C  
40  
J
MT2 POSITIVE  
MT2 NEGATIVE  
0.1  
5
-ꢀ40  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
-ꢀ10  
20  
50  
80  
110 125  
V , INSTANTANEOUS ON‐STATE VOLTAGE (VOLTS)  
T
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 3. On−State Characteristics  
Figure 5. Hold Current Variation  
4

MAC15M, MAC15N  
100  
1
OFF‐STATE VOLTAGE = 12 V  
R =
 
140
W  
L
Q2  
Q3  
Q1  
Q1  
Q3  
Q2  
OFF‐STATE VOLTAGE = 12 V  
R =
 
140
W  
L
1
-ꢀ40  
0.5  
-ꢀ40  
-ꢀ10  
20  
50  
80  
110 125  
-ꢀ10  
+20  
50  
80  
110 125  
T , JUNCTION TEMPERATURE (
°
C)  
J
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 6. Typical Holding Current versus Junction  
Temperature  
Figure 7. Gate Trigger Voltage versus Junction  
Temperature  
5000  
4K  
3K  
2K  
1K  
0
100  
V =
 
800 Vpk  
D
T =
 
125
°
C  
J
T =
 
125
°
C  
100
°
C  
75
°
C  
J
10  
I
TM  
1
f =  
t
w
2 t  
w
6f I  
TM  
(di/dt)  
=
c
1000  
V
DRM  
1
10  
100  
1000  
10000  
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
R ,
 
GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS)  
G
(di/dt) , RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)  
c
Figure 8. Critical Rate of Rise of Off−State Voltage  
(Exponential)  
Figure 9. Critical Rate of Rise of  
Commutating Voltage  
L
L
1N4007  
200 V  
RMS  
ADJUST FOR  
, 60 Hz V  
MEASURE  
I
I
TM  
AC  
CHARGE  
CONTROL  
–
+
TRIGGER  
200 V  
CHARGE  
MT2  
51
W  
1N914  
MT1  
NON‐POLAR  
C
G
L
Note: Component values are for verification of rated (di/dt) .
 
See AN1048 for additional information.  
c
Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)

c  

5

MAC15M, MAC15N  
PACKAGE DIMENSIONS  
TO−220  
CASE 221A−09  
ISSUE AH  
NOTES:  
1. DIMENSIONING
 
AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING
 
DIMENSION: INCH.  
3. DIMENSION
 
Z DEFINES A ZONE WHERE ALL  
BODY AND LEAD IRREGULARITIES ARE  
ALLOWED.  
SEATING  
PLANE  
−T−  
C
S
B
F
T
INCHES  
DIM MIN
 
MAX  
MILLIMETERS  
4
1
MIN  
14.48  
9.66  
4.07  
0.64  
3.61  
2.42  
2.80  
0.36  
12.70  
1.15  
4.83  
2.54  
2.04  
1.15  
5.97  
0.00  
1.15  
—  
MAX  
15.75  
10.53  
4.83  
0.96  
4.09  
2.66  
4.10  
0.61  
14.27  
1.52  
5.33  
3.04  
2.79  
1.39  
6.47  
1.27  
—  
A
B
C
D
F
0.570  
0.380  
0.160  
0.025  
0.142  
0.095  
0.110  
0.014  
0.500  
0.045  
0.190  
0.100  
0.080  
0.045  
0.235  
0.000  
0.045  
—  
0.620  
0.415  
0.190  
0.038  
0.161  
0.105  
0.161  
0.024  
0.562  
0.060  
0.210  
0.120  
0.110  
0.055  
0.255  
0.050  
—  
A
K
Q
Z
2
3
U
H
G
H
J
K
L
N
Q
R
S
T
L
R
J
V
G
U
V
Z
D
0.080  
2.04  
N
STYLE 4:  
PIN 1.
 
MAIN TERMINAL 1  
2. MAIN
 
TERMINAL 2  
3. GATE  
4. MAIN
 
TERMINAL 2  
ON Semiconductor and the  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.  
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed  
at

. SCILLC
 
reserves the right to make changes without further notice to any products herein.
 
SCILLC makes no warranty, representation  
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and  
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
 
“Typical” parameters which may be provided in SCILLC data sheets  
and/or specifications can and do vary in different applications and actual performance may vary over time.
 
All operating parameters, including “Typicals” must be validated for each  
customer application by customer’s technical experts.
 
SCILLC does not convey any license under its patent rights nor the rights of others.
 
SCILLC products are not designed, intended,  
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which  
the failure of the SCILLC product could create a situation where personal injury or death may occur.
 
Should Buyer purchase or use SCILLC products for any such unintended or  
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and  
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part.
 
SCILLC is an Equal Opportunity/Affirmative Action Employer.
 
This literature is subject to all applicable  
copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMEN
T
:  
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: 800−282−9855
T
o
ll Free  
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.
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o
ll Free USA/Canada  
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o
ll Free USA/Canada  
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: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
MAC15M/D