onsemi-MAC16HCD

Part #onsemi-MAC16HCD
Download 
onsemi-MAC16HCD
MAC16HCD, MAC16HCM,  
MAC16HCN  
Preferred Device  
T
r
iacs  
Silicon Bidirectional Thyristors  
Designed primarily for full-wave ac control applications, such as  
motor controls, heating controls or dimmers; or wherever full−wave,  
silicon gate−controlled devices are needed.  
TRIACS  
16 AMPERES RMS  
400 thru 800 VOLTS  
Features  
•
High Commutating di/dt and High Immunity to dv/dt @ 125
°
C  
•
Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3  
•
Blocking
V
o
ltage to 800
V
o
lts  
MT2  
MT1  
•
On−State Current Rating of 16 Amperes RMS at 80
°
C  
•
High Surge Current Capability − 150 Amperes  
•
Industry Standard TO−220AB Package for Ease of Design  
•
Glass Passivated Junctions for Reliability and Uniformity  
•
Pb−Free Packages are Available*  
G
MARKING  
DIAGRAM  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
MAC16HCxG  
AYWW  
Rating  
Symbol  
Value  
Unit  
Peak Repetitive Off−State Voltage (Note

)  
V
V
DRM,  
(T =
 
−40 to 125
°
C, Sine Wave,  
V
J
RRM  
TO−220AB  
CASE 221A−09  
STYLE 4  
50 to 60 Hz, Gate Open)  
MAC16HCD  
1
400  
600  
800  
2
3
MAC16HCM  
MAC16HCN  
x
A
Y
= D, M, or N  
= Assembly Location  
= Year  
On−State RMS Current  
(Full Cycle Sine Wave 50 to 60 Hz;  
I
16  
A
A
T(RMS)  
T
= 80
°
C)  
C
WW =
 
Work Week  
Peak Non-Repetitive Surge Current  
I
150  
G
= Pb−Free Package  
TSM  
(One Full Cycle, 60 Hz, T
 
= 125
°
C)  
J
2
2
Circuit Fusing Consideration (t = 8.33 ms)  
I t  
93  
20  
A sec  
PIN ASSIGNMENT  
1
Main
T
e
rminal 1  
Peak Gate Power  
P
W
W
GM  
(Pulse Width
≤
1.0
m
s, T
 
= 80
°
C)  
C
2
3
4
Main
T
e
rminal 2  
Gate  
Average Gate Power  
P
0.5  
G(AV)  
(t = 8.3 ms, T
 
= 80
°
C)  
C
Main
T
e
rminal 2  
Operating Junction
T
e
mperature Range  
Storage
T
e
mperature Range  
T
−40 to +125  
−40 to +150  
°
C  
°
C  
J
T
stg  
ORDERING INFORMATION  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
Device  
Package  
Shipping  
MAC16HCD  
TO−220AB  
50 Units / Rail  
50 Units / Rail  
MAC16HCDG  
TO−220AB  
(Pb−Free)  
1. V  
and V  
for all types can be applied on a continuous basis. Blocking  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
DRM  
RRM  
MAC16HCM  
TO−220AB  
50 Units / Rail  
50 Units / Rail  
MAC16HCMG  
TO−220AB  
(Pb−Free)  
MAC16HCN  
TO−220AB  
50 Units / Rail  
50 Units / Rail  
MAC16HCNG  
TO−220AB  
(Pb−Free)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting
T
e
chniques  
Reference Manual, SOLDERRM/D.  
Preferred
devices are recommended choices for future use  
and best overall value.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
December, 2005 − Rev. 1  
MAC16HC/D  
 

MAC16HCD, MAC16HCM, MAC16HCN  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Value  
Unit  
Thermal Resistance,  
Junction−to−Case  
Junction−to−Ambient  
R
R
2.2  
62.5  
°
C/W  
q
JC  
JA  
q
Maximum Lead
T
e
mperature for Soldering Purposes 1/8
″
from Case for 10 Seconds  
T
260  
°
C  
L
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted; Electricals apply in both directions)  
J
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Peak Repetitive Blocking Current  
T =
 
25
°
C  
T =
 
125
°
C  
J
I
,
DRM  
−
−
−
−
0.01  
2.0  
mA  
J
(V =
 
Rated V
 
, V  
DRM  
, Gate Open)  
RRM  
I
RRM  
D
ON CHARACTERISTICS  
Peak On−State V

(I =
 
“
21 A Peak)  
V
−
−
1.6  
V
TM  
TM  
Gate Trigger Current (Continuous dc) (V
 
= 12 V, R
 
= 100
W
)  
I
mA  
D
L
GT  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
10  
10  
10  
16  
18  
22  
50  
50  
50  
Holding Current (V
 
= 12 V, Gate Open, Initiating Current =
“
150 mA)  
I
−
20  
50  
mA  
mA  
D
H
Latch Current (V
 
= 12 V, I
 
= 50 mA)  
I
D
G
L
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
−
−
−
33  
36  
33  
60  
80  
60  
Gate Trigger Voltage (Continuous dc) (V
 
= 12 V, R
 
= 100
W
)  
V
V
D
L
GT  
MT2(+), G(+)  
MT2(+), G(−)  
MT2(−), G(−)  
0.5  
0.5  
0.5  
0.80  
0.73  
0.82  
1.5  
1.5  
1.5  
DYNAMIC CHARACTERISTICS  
Rate of Change of Commutating Current  
(di/dt)c  
15  
−
−
A/ms  
(V =
 
400 V, ITM = 6A, Commutating dv/dt = 20 V/
m
s, CL = 10
m
F  
D
Gate Open, T
 
= 125
°
C, f = 250 Hz, with Snubber) LL = 40 mH  
J
Critical Rate of Rise of Off−State Voltage  
dv/dt  
di/dt  
750  
−
−
−
−
V/
m
s  
A/
m
s  
(V =
 
Rated V  
, Exponential Waveform, Gate Open, T
 
= 125
°
C)  
DRM J  
D
Repetitive Critical Rate of Rise of On-State Current  
10  
IPK = 50 A; PW = 40
m
sec; diG/dt = 200 mA/
m
sec; f = 60 Hz  
2. Pulse
 
T
e
st: Pulse Width
≤
2.0 ms, Duty Cycle
≤
2%.  
2
 

MAC16HCD, MAC16HCM, MAC16HCN  
Voltage Current Characteristic of Triacs  
(Bidirectional Device)  
+ Current  
Quadrant 1  
Main
T
e
rminal 2 +  
Symbol  
Parameter  
V
TM  
V
Peak Repetitive Forward Off State Voltage  
Peak Forward Blocking Current  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
V
Peak Repetitive Reverse Off State Voltage  
Peak Reverse Blocking Current  
RRM  
RRM  
I
RRM  
V
Maximum On State Voltage  
Holding Current  
+ Voltage  
off state  
TM  
I
I
at V  
H
DRM  
DRM  
I
H
Quadrant 3  
Main
T
e
rminal 2 −  
V
TM  
Quadrant Definitions for a Triac  
MT2 POSITIVE  
(Positive Half Cycle)  
+
(+) MT2  
(+) MT2  
Quadrant II  
Quadrant I  
(−) I  
(+) I  
GT  
GT  
GATE  
GATE  
MT1  
MT1  
REF  
REF  
I
−
+ I  
GT  
GT  
(−) MT2  
(−) MT2  
Quadrant III  
Quadrant IV  
(+) I  
(−) I  
GT  
GT  
GATE  
GATE  
MT1  
REF  
MT1  
REF  
−
MT2 NEGATIVE  
(Negative Half Cycle)  
All polarities are referenced to MT1.  
With in−phase signals (using standard AC lines) quadrants I and III are used.  
3

                                             
−
                                                       
5
−
                                                                 
40  
2
10  
5
20 35 50 65 80 95
 
110 125  
5
20 35 50 65 80 95
 
110 125  
−
                                              
−
                                                       
5
−
                                                                 
40  
2
10  
5
20  
35 50 65 80 95
 
110 125  
−ꢀ40 −ꢀ25 −ꢀ10  
5
20 35 50  
65 80 95
 
110 125  
MAC16HCD, MAC16HCM, MAC16HCN  
100  
1.10  
Q3  
1.00  
Q3  
Q2  
Q1  
0.90  
Q2  
Q1  
0.80  
10  
0.70  
0.60  
0.50  
1
−
0.40  
−ꢀ40 −ꢀ25 −ꢀ10  
T , JUNCTION TEMPERATURE (
°
C)  
J
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 2. Typical Gate Trigger Voltage  
versus Junction Temperature  
Figure 1. Typical Gate Trigger Current  
versus Junction Temperature  
100  
10  
1
100  
10  
1
Q2  
Q1  
Q3  
MT2 NEGATIVE  
MT2 POSITIVE  
T , JUNCTION TEMPERATURE (
°
C)  
J
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 4. Typical Latching Current  
versus Junction Temperature  
Figure 3. Typical Holding Current  
versus Junction Temperature  
24  
125  
DC  
22  
20  
18  
16  
14  
12  
10  
8
120  
115  
110  
105  
100  
95  
180
°  
120
°  
60
°
, 30
°  
90
°  
120
°  
90  
180
°  
90
°  
DC  
60
°  
85  
6
30
°  
80  
4
75  
70  
2
0
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
I
, RMS ON-STATE CURRENT (AMP)  
I
T(AV)  
, AVERAGE ON-STATE CURRENT (AMP)  
T(RMS)  
Figure 5. Typical RMS Current Derating  
Figure 6. On-State Power Dissipation  
4

MAC16HCD, MAC16HCM, MAC16HCN  
1
100  
TYPICAL @  
T =
 
25
°
C  
J
MAXIMUM @ T
 
= 125
°
C  
J
10  
0.1  
MAXIMUM @ T
 
= 25
°
C  
J
1
0.01  
0.1  
1
10  
100  
1000  
10000  
t, TIME (ms)  
Figure 8. Typical Thermal Response  
0.1  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
V , INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)  
T
Figure 7. Typical On-State Characteristics  
5

MAC16HCD, MAC16HCM, MAC16HCN  
PACKAGE DIMENSIONS  
TO−220AB  
CASE 221A−09  
ISSUE AA  
NOTES:  
1. DIMENSIONING
 
AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
SEATING  
PLANE  
−T−  
2. CONTROLLING
 
DIMENSION: INCH.  
3. DIMENSION
 
Z DEFINES A ZONE WHERE ALL  
BODY AND LEAD IRREGULARITIES ARE  
ALLOWED.  
C
B
F
T
S
4
INCHES  
DIM MIN
 
MAX  
MILLIMETERS  
MIN  
14.48  
9.66  
4.07  
0.64  
3.61  
2.42  
2.80  
0.46  
12.70  
1.15  
4.83  
2.54  
2.04  
1.15  
5.97  
0.00  
1.15  
−−−  
MAX  
15.75  
10.28  
4.82  
0.88  
3.73  
2.66  
3.93  
0.64  
14.27  
1.52  
5.33  
3.04  
2.79  
1.39  
6.47  
1.27  
−−−  
A
K
Q
Z
A
B
C
D
F
0.570  
0.380  
0.160  
0.025  
0.142  
0.095  
0.110  
0.018  
0.500  
0.045  
0.190  
0.100  
0.080  
0.045  
0.235  
0.000  
0.045  
0.620  
0.405  
0.190  
0.035  
0.147  
0.105  
0.155  
0.025  
0.562  
0.060  
0.210  
0.120  
0.110  
0.055  
0.255  
0.050  
−−−  
1
2
3
U
H
G
H
J
K
L
L
R
N
Q
R
S
T
V
J
G
D
U
V
Z
N
−−− 0.080  
2.04  
STYLE 4:  
PIN 1.
 
MAIN TERMINAL 1  
2. MAIN
 
TERMINAL 2  
3. GATE  
4. MAIN
 
TERMINAL 2  
ON Semiconductor
and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
 
SCILLC reserves the right to make changes without further notice  
to any products herein.
 
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
 
All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
 
SCILLC does not convey any license under its patent rights  
nor the rights of others.
 
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
 
Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
 
SCILLC is an Equal  
Opportunity/Affirmative Action Employer.
 
This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMEN
T
:  
N. American Technical Support
: 800−282−9855
T
o
ll Free  
USA/Canada  
ON Semiconductor Website

Literature Distribution Center for ON Semiconductor  
P
.
O. Box 61312, Phoenix, Arizona 85082−1312 USA  
Phone
: 480−829−7710 or 800−344−3860
T
o
ll Free USA/Canada  
Fax
: 480−829−7709 or 800−344−3867
T
o
ll Free USA/Canada  
Email
: orderlit@onsemi.com  
Japan
: ON Semiconductor, Japan Customer Focus Center  
2−9−1 Kamimeguro, Meguro−ku,
T
o
kyo, Japan 153−0051  
Phone
: 81−3−5773−3850  
For additional information, please contact your  
local Sales Representative.  
MAC16HC/D