onsemi-MC1496BDR2G
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MC1496, MC1496B
Balanced Modulators/
Demodulators
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier).
Typical applications include suppressed carrier and amplitude
modulation, synchronous detection, FM detection, phase detection,
and chopper applications. See ON Semiconductor Application Note
AN531 for additional design information.
SOIC
−
14
D SUFFIX
CASE 751A
14
Features
1
•
Excellent Carrier Suppression
−
65 dB typ @ 0.5 MHz
−
50 dB typ @ 10 MHz
•
Adjustable Gain and Signal Handling
•
Balanced Inputs and Outputs
•
High Common Mode Rejection
−
85 dB Typical
PDIP
−
14
P SUFFIX
CASE 646
14
•
This Device Contains 8 Active Transistors
•
Pb
−
Free Package is Available*
1
PIN CONNECTIONS
14
13
12
11
10
9
1
2
3
4
5
6
7
Signal Input
Gain Adjust
Gain Adjust
Signal Input
Bias
V
EE
N/C
Output
N/C
Carrier Input
N/C
Output
8
N/C
Input Carrier
ORDERING INFORMATION
See detailed ordering and shipping information in the package
DEVICE MARKING INFORMATION
See general marking information in the device marking
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006
−
Rev. 10
MC1496/D
MC1496, MC1496B
0
I
C
I
S
= 500 kHz
= 1.0 kHz
20
40
60
I
C
= 500 kHz, I
= 1.0 kHz
S
499 kHz
500 kHz
501 kHz
Figure 1. Suppressed Carrier Output
Waveform
Figure 2. Suppressed Carrier Spectrum
10
I
C
I
S
= 500 kHz
= 1.0 kHz
8.0
6.0
4.0
2.0
0
I
C
I
S
= 500 kHz
= 1.0 kHz
499 kHz
500 kHz
501 kHz
Figure 3. Amplitude Modulation
Output Waveform
Figure 4. Amplitude
−
Modulation Spectrum
MAXIMUM RATINGS
(T =
25
°
C, unless otherwise noted.)
A
Rating
Symbol
Value
Unit
Applied Voltage
ꢀ
V
30
Vdc
(V6
−
V8, V10
−
V1, V12
−
V8, V12
−
V10, V8
−
V4, V8
−
V1, V10
−
V4, V6
−
V10, V2
−
V5, V3
−
V5)
Differential Input Signal
V8
−
V10
V4
−
V1
+5.0
Vdc
±
(
5
+
I
5R )
e
Maximum Bias Current
I
10
mA
5
Thermal Resistance, Junction
−
to
−
Air
Plastic Dual In
−
Line Package
R
ꢁ
JA
100
°
C/W
Operating Ambient
T
e
mperature Range
MC1496
MC1496B
T
A
°
C
0 to +70
−
40 to +125
Storage
T
e
mperature Range
T
stg
°
C
−
65 to +150
Electrostatic Discharge Sensitivity (ESD)
Human Body Model (HBM)
Machine Model (MM)
ESD
V
2000
400
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
MC1496, MC1496B
ELECTRICAL CHARACTERISTICS
(V =
12 Vdc, V
=
−
8.0 Vdc, I5 = 1.0 mAdc, R
= 3.9 k
ꢂ
, R
= 1.0 k
ꢂ
, T
= T
to T
,
CC
EE
L
e
A
low
high
Characteristic
Fig.
Note
Symbol
Min
Typ
Max
Unit
Carrier Feedthrough
5
1
V
ꢃ
V
r
m
s
CFT
V
= 60 mVrms sine wave and
f
f
= 1.0 kHz
= 10 MHz
−
−
40
−
−
C
C
C
offset adjusted to zero
= 300 mVpp square wave:
140
V
mVrms
dB
C
offset adjusted to zero
offset not adjusted
f
f
= 1.0 kHz
= 1.0 kHz
−
−
0.04
20
0.4
200
C
C
Carrier Suppression
= 10 kHz, 300 mVrms
5
8
2
8
V
CS
f
S
f
f
= 500 kHz, 60 mVrms sine wave
= 10 MHz, 60 mVrms sine wave
40
−
65
50
−
−
C
C
k
Transadmittance Bandwidth (Magnitude) (R
= 50
ꢂ
)
Carrier Input Port, V
= 60 mVrms sine wave
BW
MHz
L
3dB
−
−
300
80
−
−
C
f
= 1.0 kHz, 300 mVrms sine wave
S
Signal Input Port, V
= 300 mVrms sine wave
S
|V |
= 0.5 Vdc
C
Signal Gain (V
= 100 mVrms, f = 1.0 kHz;
|
V
|
= 0.5 Vdc)
10
6
3
A
VS
2.5
3.5
−
V/V
S
C
Single
−
Ended Input Impedance, Signal Port, f = 5.0 MHz
Parallel Input Resistance
Parallel Input Capacitance
−
r
−
−
200
2.0
−
−
k
ꢂ
pF
ip
c
ip
Single
−
Ended Output Impedance, f = 10 MHz
Parallel Output Resistance
6
7
−
−
r
−
−
40
−
−
k
ꢂ
op
oo
Parallel Output Capacitance
c
5.0
pF
ꢃ
A
Input Bias Current
I
bS
bC
−
−
12
12
30
30
I1
)
I4
I8
)
I10
I
+
; I
+
I
bS
bC
2
2
Input Offset Current
= I1
−
I4; I
= I8
−
I10
7
7
−
−
⎥
I
ioC
⎥
⎥
−
−
0.7
0.7
7.0
7.0
ꢃ
A
ioS
I
I
ioS
ioC
Average
T
e
mperature Coefficient of Input Offset Current
(T =
−
55
°
C to +125
°
C)
A
⎥
TC
⎥
Iio
−
2.0
−
nA/
°
C
Output Offset Current (I6
−
I9)
7
7
−
−
⎥
I
⎥
−
−
14
90
80
ꢃ
A
oo
Average
T
e
mperature Coefficient of Output Offset Current
(T =
−
55
°
C to +125
°
C)
A
⎥
TC
⎥
−
nA/
°
C
Ioo
Common
−
Mode Input Swing, Signal Port, f
= 1.0 kHz
9
9
4
−
−
−
6
CMV
ACM
−
−
−
−
5.0
−
85
8.0
8.0
−
−
−
−
Vpp
dB
S
Common
−
Mode Gain, Signal Port, f
= 1.0 kHz, |V
|= 0.5 Vdc
S
C
Common
−
Mode Quiescent Output Voltage (Pin 6 or Pin 9)
10
10
7
V
out
Vpp
Vpp
mAdc
Differential Output Voltage Swing Capability
V
out
Power Supply Current
I6 +I12
Power Supply Current
I14
I
I
−
−
2.0
3.0
4.0
5.0
CC
EE
DC Power Dissipation
7
5
P
−
33
−
mW
D
1. T
= 0
°
C for MC1496
=
−
40
°
C for MC1496B
T
= +70
°
C for MC1496
= +125
°
C for MC1496B
low
high
3
MC1496, MC1496B
GENERAL OPERATING INFORMATION
Carrier Feedthrough
S
Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied
(signal voltage = 0).
Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
a maximum value of 1.0 V peak.
Common Mode Swing
The common
−
mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.
Carrier Suppression
Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.
Power Dissipation
Power dissipation, P , within the integrated circuit
D
Carrier suppression is very dependent on carrier input
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
package should be calculated as the summation of the
voltage
−
current products at each port, i.e. assuming
V12 = V6, I5 = I6 = I12 and ignoring base current,
=
P
2 I5 (V6
−
V14) + I5)V5
−
V14 where subscripts refer
D
to pin numbers.
Design Equations
The following is a partial list of design equations needed
to operate the circuit with other supply voltages and input
conditions.
A. Operating Current
The internal bias currents are set by the conditions at Pin
5.
Assume:
Carrier feedthrough is independent of signal level, V .
S
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal
−
input transistor pair
−
or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit
carrier suppression and minimum spurious sideband
generation.
I5 = I6 = I12,
I
t
t
I for
all transistors
B
C
then :
where: R5
is the resistor between
where:
Pin 5 and ground
where:
ꢄ
= 0.75 at T
A
= +25
°
C
V
*
*
ꢄ
R5
+
*
500
ꢂ
I5
The MC1496 has been characterized for the condition
I =
1.0 mA and is the generally recommended value.
5
At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
B. Common
−
Mode Quiescent Output
V
o
ltage
V6 = V12 = V+
−
I5 R
L
Biasing
Signal Gain and Maximum Input Level
Signal gain (single
−
ended) at low frequencies is defined
as the voltage gain,
The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector
−
base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
R
V
o
26 mV
I5(mA)
L
A
+
+
where r
+
e
VS
V
R
)
2r
e
e
S
30 Vdc
w
[(V6, V12)
−
(V8, V10)]
w
2 Vdc
30 Vdc
w
[(V8, V10)
−
(V1, V4)]
w
2.7 Vdc
30 Vdc
w
[(V1, V4)
−
(V5)]
w
2.7 Vdc
A constant dc potential is applied to the carrier input
terminals to fully switch two of the upper transistors “on”
and two transistors “off” (V
= 0.5 Vdc). This in effect
C
The foregoing conditions are based on the following
approximations:
forms a cascode differential amplifier.
Linear operation requires that the signal input be below a
V6 = V12, V8 = V10, V1 = V4
critical value determined by R
and the bias current I5.
E
V
S
p
I5 R
E
(Volts peak)
4
MC1496, MC1496B
Negative Supply
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
V
EE
should be dc only. The insertion of an RF choke in
series with V
can enhance the stability of the internal
EE
current sources.
Transadmittance Bandwidth
Signal Port Stability
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source
−
tuned
circuits that cause the oscillation.
i
(each sideband)
o
+
V
+
0
o
⎥
ꢅ
21C
v (signal)
s
Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
Signal Input
(Pins 1 and 4)
i
(signal)
o
s
+
V
+
0.5 Vdc,
V
+
0
c o
⎥
ꢅ
21S
510
v (signal)
10 pF
Coupling and Bypass Capacitors
reactance of less than 5.0
ꢂ
at the carrier frequency.
An alternate method for low
−
frequency applications is to
insert a 1.0 k
ꢂ
resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation
of carrier suppression.
Output Signal
The output signal is taken from Pins 6 and 12 either
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single
−
ended output connection.
TEST CIRCUITS
V
CC
12 Vdc
R =
1.0 k
e
1.0 k
1.0 k
2
R
2
3
5
e
0.5 V
R
3.9 k
R
L
3.9 k
8
10
L
C1
0.1
ꢃ
F
51
−
+
1.0 k
+ꢀV
out
−ꢀV
o
3
5
C
2
6
Carrier
Z
8
10
1
MC1496
1
4
0.1
ꢃ
F
Input
V
I9 I6
Z
o
in
+ꢀV
−ꢀV
o
o
12
C
S
6
MC1496
V
14
4
12
Modulating
Signal Input
6.8 k
14
10 k
10 k
51
50 k
51
I5
6.8 k
−8.0 Vdc
I10
R1
−
V
Carrier Null
NOTE:
Shielding of input and output leads may be needed
−8.0 Vdc
to properly perform these tests.
V
EE
Figure 5. Carrier Rejection and Suppression
Figure 6. Input
−
Output Impedance
V
CC
V
CC
12 Vdc
1.0 k
1.0 k
2
12 Vdc
R
2.0 k
e
R =
1.0 k
e
51
1.0 k
I7
0.1
ꢃ
F
0.01
ꢃ
F
1.0 k
3
2
3
5
Carrier
Input
V
50 50
8
10
2.0 k
8
10
0.1
ꢃ
F
I6
I9
+ꢀV
I8
I1
I4
o
C
S
6
MC1496
6
1
4
1.0 k
MC1496
V
1
4
−ꢀV
o
Modulating
Signal Input
12
12
5
14
10 k
10 k
50 k
51
51
14
I10
6.8 k
6.8 k
−
V
Carrier Null
−8.0 Vdc
−8.0 Vdc
V
V
EE
EE
Figure 8. Transconductance Bandwidth
Figure 7. Bias and Offset Currents
5
MC1496, MC1496B
V
CC
V
CC
12 Vdc
12 Vdc
R =
1.0 k
e
R =
1.0 k
e
1.0 k
0.5 V
1.0 k
0.5 V
3.9 k
3.9 k
3.9 k
3.9 k
2
3
5
2
3
5
8
10
1
1.0 k
8
10
1
−
+
+
−
1.0 k
+ꢀV
o
+ꢀV
o
o
6
MC1496
6
MC1496
−ꢀV
V
S
o
−ꢀV
V
4
S
12
4
12
14
14
50
I5 =
1.0 mA
6.8 k
6.8 k
50
⎥
ꢀ
V
⎥
o
A
+
20 logꢁ
CM
−8.0 Vdc
V
S
−8.0 Vdc
V
EE
V
EE
Figure 9. Common Mode Gain
Figure 10. Signal Gain and Output Swing
TYPICAL CHARACTERISTICS
C
V
= 60 mVrms, f
= 1.0 kHz, V
= 300 mVrms, T
= 25
°
C, unless otherwise noted.
C
S
S
A
1.0 M
2.0
1.6
500
+r
ip
−r
ip
100
50
Signal Input = 600 mV
400 mV
1.2
0.8
300 mV
200 mV
100 mV
10
5.0
0.4
0
1.0
1.0
0
50
100
150
200
5.0
10
50
100
V ,
CARRIER LEVEL (mVrms)
C
f, FREQUENCY (MHz)
Figure 11. Sideband Output versus
Carrier Levels
Figure 12. Signal
−
Port Parallel
−
Equivalent
Input Resistance versus Frequency
140
120
14
5.0
4.0
12
10
100
80
3.0
2.0
r
op
8.0
6.0
4.0
60
c
op
40
1.0
0
20
0
2.0
0
1.0
2.0
5.0
10
20
50
100
0
1.0
10
100
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 13. Signal
−
Port Parallel
−
Equivalent
Figure 14. Single
−
Ended Output Impedance
Input Capacitance versus Frequency
versus Frequency
6
f
C
−
−
10
20
MC1496, MC1496B
TYPICAL CHARACTERISTICS
(continued)
C
V
= 60 mVrms, f
= 1.0 kHz, V
= 300 mVrms, T
= 25
°
C, unless otherwise noted.
C
S S
A
0
1.0
0.9
Signal Port
Side Band
10
20
30
40
50
0.8
0.7
0.6
0.5
0.4
MC1496
(70
°
C)
Sideband Transadmittance
I
ꢁ(EachꢁSideband)
out
ꢅ
+
+
ꢁ
V
out
+
0
21
⎥
V
ꢁ(Signal)
in
0.3
0.2
Signal Port Transadmittance
I
60
70
out
ꢅ
ꢁV
+
0ꢁꢁ|V |
+
0.5ꢁVdc
out
21
0.1
0
C
⎥
V
in
1.0
f ,
CARRIER FREQUENCY (MHz)
−75 −50
−25
0
25
50
75 100
125 150
175
0.1
10
100
1000
C
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 15. Sideband and Signal Port
Transadmittances versus Frequency
Figure 16. Carrier Suppression
versus Temperature
0
20
10
0
R =
3.9 k
R =
500
ꢂ
e
L
10
20
30
40
50
R =
3.9 k (Standard
R =
1.0 k Test Circuit)
e
L
R =
3.9 k
L
R =
2.0 k
e
2f
C
R =
500
ꢂ
L
|V |
= 0.5 Vdc
C
R =
1.0 k
e
R
60
70
3f
L
C
A
+
V
R
)
2r
e
e
−ꢀ30
0.01
0.1
1.0
10
100
0.05
0.1
0.5 1.0
5.0 10
50
f, FREQUENCY (MHz)
f ,
CARRIER FREQUENCY (MHz)
C
Figure 17. Signal
−
Port Frequency Response
Figure 18. Carrier Suppression
versus Frequency
10
0
10
20
30
1.0
0.1
40
50
60
70
80
f
f
±
3f
±
2f
C
S
S
C
0.01
0.05 0.1
0.5 1.0
5.0
10
50
0
200
400
600
800
f ,
CARRIER FREQUENCY (MHz)
C
V ,
INPUT SIGNAL AMPLITUDE (mVrms)
S
Figure 19. Carrier Feedthrough
versus Frequency
Figure 20. Sideband Harmonic Suppression
versus Input Signal Level
7
MC1496, MC1496B
0
10
20
30
40
50
0
10
3f
±
f
C
S
20
30
f
= 10 MHz
= 500 kHz
C
2f
±
f
C
S
40
50
2f
±
2f
C
f
C
S
60
70
60
70
0.05 0.1
0.5 1.0
5.0
10
50
0
100
200
300
400
500
f ,
CARRIER FREQUENCY (MHz)
C
V ,
CARRIER INPUT LEVEL (mVrms)
C
Figure 21. Suppression of Carrier Harmonic
Sidebands versus Carrier Frequency
Figure 22. Carrier Suppression versus
Carrier Input Level
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is
components and have an amplitude which is a function of the
product of the input signal amplitudes.
This circuit consists of an upper quad differential amplifier
driven by a standard differential amplifier with dual current
sources. The output collectors are cross
−
coupled so that
full
−
wave balanced multiplication of the two input voltages
occurs. That is, the output signal is a constant times the
product of the two input signals.
Mathematical analysis of linear ac signal multiplication
indicates that the output spectrum will consist of only the sum
and difference of the two input frequencies. Thus, the device
may be used as a balanced modulator, doubly balanced mixer,
product detector, frequency doubler, and other applications
requiring these particular output signal characteristics.
The lower differential amplifier has its emitters connected
to the package pins so that an external emitter resistance may
be used. Also, external load resistors are employed at the
device output.
For high
−
level operation at the carrier input port and
linear operation at the modulating signal port, the output
signal will contain sum and difference frequency
components of the modulating signal frequency and the
fundamental and odd harmonics of the carrier frequency.
The output amplitude will be a constant times the
modulating signal amplitude. Any amplitude variations in
the carrier signal will not appear in the output.
The linear signal handling capabilities of a differential
amplifier are well defined. With no emitter degeneration, the
maximum input voltage for linear operation is
approximately 25 mV peak. Since the upper differential
amplifier has its emitters internally connected, this voltage
applies to the carrier input port for all conditions.
Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
linear operation may be approximated from the following
expression:
Signal Levels
The upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differential
amplifier is operated in a linear mode for most applications.
For low
−
level operation at both input ports, the output
signal will contain sum and difference frequency
(−) 12
V = (I5) (R
E
) volts peak.
This expression may be used to compute the minimum
value of R
for a given input voltage amplitude.
E
1.0 k
1.0 k
0.1
ꢃ
F
12 Vdc
V ,
o
Output
(+) 6
R
3.9 k
R
L
3.9 k
L
2
3
R
1.0 k
e
51
10 (−)
8
10
Carrier
Input
0.1
ꢃ
F
+V
V
V
o
C
V
C
S
6
Carrier
Input
8 (+)
4 (−)
1
4
MC1496
V
−V
o
Signal
Input
2
3
Modulating
Signal
Input
S
Gain
Adjust
12
1 (+)
10 k
51 51
10 k
50 k
14
5
Bias 5
I5
6.8 k
(Pin numbers
per G package)
500
500
500
Carrier Null
−8.0 Vdc
V
14
V
EE
EE
Figure 23. Circuit Schematic
Figure 24. Typical Modulator Circuit
8
MC1496, MC1496B
Table 1. Voltage Gain and Output Frequencies
Carrier Input Signal (V
)
Approximate Voltage Gain
Output Signal Frequency(s)
C
R
V
L
C
Low
−
level dc
High
−
level dc
Low
−
level ac
High
−
level ac
f
f
M
M
KT
)
2r )
ǒ Ǔ
2(R
e
q
E
R
L
R
)
2r
e
E
R
V (rms)
L
C
f
±
f
M
C
KT
Ǹ
2 2
ǒ
q
Ǔ
(R
)
2r )
e
E
0.637 R
L
e
f
C
±
f ,
3f
±
f ,
5f
±
f , . . .
M C M C M
R
)
2r
E
2. Low
−
level Modulating Signal, V
, assumed in all cases. V
is Carrier Input Voltage.
M
C
3. When
the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs,
+ f
and f
−
f .
f
C
M
C
M
4. All
gain expressions are for a single
−
ended output. For a differential output connection, multiply each expression by two.
5. R =
Load resistance.
L
6. R
= Emitter resistance between Pins 2 and 3.
E
7. r =
Transistor dynamic emitter resistance, at 25
°
C;
26 mV
e
re
[
I
(mA)
5
8. K
= Boltzmann
′
s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
The gain from the modulating signal input port to the
output is the MC1496 gain parameter which is most often of
interest to the designer. This gain has significance only when
the lower differential amplifier is operated in a linear mode,
but this includes most applications of the device.
As previously mentioned, the upper quad differential
amplifier may be operated either in a linear or a saturated
mode. Approximate gain expressions have been developed
for the MC1496 for a low
−
level modulating signal input and
the following carrier input conditions:
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the
proper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Therefore, the modulator may be modified for AM
operation by changing two resistor values in the null circuit
Product Detector
The MC1496 makes an excellent SSB product detector
1) Low
−
level dc
2) High
−
level dc
3) Low
−
level ac
4) High
−
level ac
This product detector has a sensitivity of 3.0
ꢃ
V and a
dynamic range of 90 dB when operating at an intermediate
frequency of 9.0 MHz.
The detector is broadband for the entire high frequency
range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1
ꢃ
F capacitors on Pins 8 and 10 should
be increased to 1.0
ꢃ
F. Also, the output filter at Pin 12 can
be tailored to a specific intermediate frequency and audio
amplifier input impedance.
As in all applications of the MC1496, the emitter
resistance between Pins 2 and 3 may be increased or
decreased to adjust circuit gain, sensitivity, and dynamic
range.
This circuit may also be used as an AM detector by
introducing carrier signal at the carrier input and an AM
signal at the SSB input.
frequency components contained in the output signal.
APPLIC
A
T
IONS INFORMATION
Double sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1496 with a single dc supply voltage instead of dual
supplies. Figure 25
shows a balanced modulator designed
for operation with a single 12 Vdc supply. Performance of
this circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 26 may be used as an
amplitude modulator with a minor modification.
The carrier signal may be derived from the intermediate
frequency signal or generated locally. The carrier signal may
9
MC1496, MC1496B
be introduced with or without modulation, provided its level
and a tuned output very high frequency (VHF) doubler,
respectively.
is sufficiently high to saturate the upper quad differential
amplifier. If the carrier signal is modulated, a 300 mVrms
input level is recommended.
Phase Detection and FM Detection
The MC1496 will function as a phase detector. High
−
level
input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1496 will deliver an output
which is a function of the phase difference between the two
input signals.
An FM detector may be constructed by using the phase
detector principle. A tuned circuit is added at one of the
inputs to cause the two input signals to vary in phase as a
function of frequency. The MC1496 will then provide an
output which is a function of the input signal frequency.
Doubly Balanced Mixer
The MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and output
networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mVrms.
tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
TYPICAL APPLICATIONS
V
CC
1.0 k
+
820
0.1
ꢃ
F
1.3 k
12 Vdc
V
12 Vd
CC
1.0 k
1.0 k
3.0 k
6
3.0 k
1.0 k
2
3
25
ꢃ
F
DSB
51
R
L
3.9 k
8
10
1
R
1.0 k
R
3.9
0.1
ꢃ
F
15 V
e
L
0.1
ꢃ
F
2
3
Carrier Input
60 mVrms
51
Output
0.1
ꢃ
F
8
10
1
0.1
ꢃ
F
+
MC1496
V
C
S
6
Carrier
4
MC1496
Modulating
Input
−
+
12
4
V
14
5
−
Signal Input
10
ꢃ
F
300 mVrms
15 V
25
ꢃ
F
15 V
Modulating
Signal
Input
12
10 k
10 k
50 k
51 51
14
10 k
5
+
−
Carrier
10 k
10 k
100 100
I5
6.8 k
Null
R1
Carrier Null
50 k
V
EE
−8.0 Vdc
Figure 25. Balanced Modulator
(12 Vdc Single Supply)
Figure 26. Balanced Modulator
−
Demodulator
V
CC
V
CC
820
1.3 k
3
12 Vdc
1.0 k
1.0 k
12 Vdc
0.1
ꢃ
F
R
3.9 k
L
0.1
ꢃ
F
1.0 k
R
1.0 k
e
R
3.9 k
2
3
5
100
L
51
3.0 k
6
3.0 k
2
8
10
1
51
8
10
1
0.1
ꢃ
F
V
C
6
0.1
ꢃ
F
Carrier Input
300 mVrms
+V
o
0.005
ꢃ
F
Carrier
Input
MC1496
MC1496
AF
Outp
V
4
S
1.0
ꢃ
F
1.0 k
SSB Input
1.0 k
4
0.1
ꢃ
F
Modulating
Signal
12
−V
o
12
750
750
51 51
14
R
q
10
1.0 k
14
5
L
0.1
ꢃ
F
Input
50 k
0.005 0.005
ꢃ
F
ꢃ
F
10 k
6.8 k
15
V
EE
Carrier Adjust
−8.0 Vdc
Figure 27. AM Modulator Circuit
Figure 28. Product Detector
(12 Vdc Single Supply)
10
MC1496, MC1496B
V
CC
12 Vdc
V
CC
1.0 k
1.0 k
+
−
100
ꢃ
F
25 Vdc
+8.0 Vdc
1.0 k
0.01
ꢃ
F
1.0 k
0.001
ꢃ
F
3.9 k
6
3
2
RFC
100
ꢃ
H
Local
Oscillator
Input
3
8
2
3.9 k
Outp
1.0 k
C2
8
10
1
51
0.001
ꢃ
F
100
10
6
C2
100
ꢃ
F
15 Vdc Max
−
+
100 mVrms
RF Input
Input
MC1496
MC1496
0.001
ꢃ
F
9.5
ꢃ
F
9.0 MHz
15 mVrms
Output
100
ꢃ
F 15 Vdc
1
4
4
10 k
12
12
L1
R =
50
ꢂ
L
51
14
5
5.0−80
pF
6.8 k
−8.0 Vdc
10 k
50 k
51
90−480 pF
14
5
10 k
10 k
100
100
Null Adjust
50 k
V
EE
6.8 k
I5
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound
on Micrometals Type 44
−
6
T
o
roid Core.
V
EE
Balance
−8.0 Vdc
Figure 29. Doubly Balanced Mixer
Figure 30. Low
−
Frequency Doubler
(Broadband Inputs, 9.0 MHz Tuned Output)
V
CC
+
+8.0 Vdc
V
1.0 k
1.0 k
0.001
18 pF
ꢃ
F
0.001
R
L1
18 nH
FC
0.68
ꢃ
H
ꢃ
F
100
2
3
5
1.0−10 pF
300 MHz
Output
6
8
10
1
0.001
ꢃ
F
R =
50
ꢂ
L
150 MHz
Input
1.0−10 pF
MC1496
4
12
10 k
10 k
100
14
100
50 k
6.8 k
L1 = 1 Turn AWG
No. 18 Wire, 7/32
″
ID
Balance
V
EE
−8.0 Vdc
Figure 31. 150 to 300 MHz Doubler
Frequency
Balanced Modulator Spectrum
DEFINITIONS
f
f
Carrier Fundamental
Modulating Signal
f
C
±
nf
S
Fundamental Carrier Sideband Harmonics
Carrier Harmonics
C
nf
C
S
f
C
±
f
S
Fundamental Carrier Sidebands
nf
±
nf
C S
Carrier Harmonic Sidebands
11
MC1496, MC1496B
ORDERING INFORMATION
Device
†
Package
Shipping
MC1496D
SOIC
−
14
55 Units/Rail
MC1496DG
SOIC
−
14
(Pb
−
Free)
MC1496DR2
SOIC
−
14
2500
T
a
pe & Reel
MC1496DR2G
SOIC
−
14
(Pb
−
Free)
MC1496P
PDIP
−
14
MC1496PG
PDIP
−
14
(Pb
−
Free)
25 Units/Rail
MC1496P1
PDIP
−
14
MC1496P1G
PDIP
−
14
(Pb
−
Free)
MC1496BD
SOIC
−
14
55 Units/Rail
2500
T
a
pe & Reel
25 Units/Rail
MC1496BDG
SOIC
−
14
(Pb
−
Free)
MC1496BDR2
SOIC
−
14
MC1496BDR2G
SOIC
−
14
(Pb
−
Free)
MC1496BP
PDIP
−
14
MC1496BPG
PDIP
−
14
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP
−
14
P SUFFIX
CASE 646
SOIC
−
14
D SUFFIX
CASE 751A
14
1
14
14
1
14
MC1496DG
AWLYWW
MC1496BDG
AWLYWW
MC1496P
AWLYYWWG
MC1496BP
AWLYYWWG
1
1
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb
−
Free Package
WL
Y
Y
, Y
WW
G
12
MC1496, MC1496B
PACKAGE DIMENSIONS
SOIC
−
14
CASE 751A
−
03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−
A
−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−
B
−
P
7 PL
M
M
0.25 (0.010)
B
7
1
G
MILLIMETERS
DIM MIN
MAX
INCHES
MIN MAX
F
R
X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−
T
−
SE
A
T
ING
PLANE
J
M
K
1.27 BSC
D
14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
13
MC1496, MC1496B
PDIP
−
14
CASE 646
−
06
ISSUE P
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING
DIMENSION: INCH.
3. DIMENSION
L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION
B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED
CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−
T
−
SE
A
T
ING
PLANE
J
_
_
K
0.015
0.039
1.01
D
14 PL
H
G
M
M
0.13 (0.005)
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
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: 800
−
282
−
9855
T
o
ll Free
USA/Canada
Literature Distribution Center for ON Semiconductor
P
.
O. Box 5163, Denver, Colorado 80217 USA
Phone
: 303
−
675
−
2175 or 800
−
344
−
3860
T
o
ll Free USA/Canada
Fax
: 303
−
675
−
2176 or 800
−
344
−
3867
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o
ll Free USA/Canada
Email
: orderlit@onsemi.com
Japan
: ON Semiconductor, Japan Customer Focus Center
2
−
9
−
1 Kamimeguro, Meguro
−
ku,
T
o
kyo, Japan 153
−
0051
Phone
: 81
−
3
−
5773
−
3850
For additional information, please contact your
local Sales Representative.
MC1496/D
