onsemi-MJF47G
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MJF47G
High Voltage Power
Transistor
Isolated Package Applications
Designed for line operated audio output amplifiers, switching power
supply drivers and other switching applications, where the mounting
surface of the device is required to be electrically isolated from the
heatsink or chassis.
NPN SILICON
POWER TRANSISTOR
1 AMPERE
Features
•
Electrically Similar to the Popular TIP47
250 VOLTS, 28 WATTS
•
250 V
CEO(sus)
•
1 A Rated Collector Current
•
No Isolating Washers Required
•
Reduced System Cost
•
UL Recognized, File #E69369, to 3500 V
•
This is a Pb
−
Free Device*
Isolation
RMS
TO
−
220 FULLPACK
CASE 221D
STYLE 2
MAXIMUM RATINGS
Rating
Collector
−
Emitter Voltage
Collector
−
Base Voltage
Emitter
−
Base Voltage
Symbol
Value
250
350
5
Unit
Vdc
Vdc
Vdc
V
1
2
V
CEO
3
V
CB
V
EB
MARKING DIAGRAM
V
ISOL
T
e
st No. 2 Per Figure 11
T
e
st No. 3 Per Figure 12
4500
3500
1500
(for 1 sec, R.H. < 30%, T
= 25
_
C)
A
Collector Current
−
Continuous
−
Peak
I
C
1
2
Adc
Adc
MJF47G
AYWW
Base Current
−
Continuous
I
B
0.6
P
28.4
W
C
D
0.227
W/
_
C
Derate above 25
_
C
T
o
tal Power Dissipation @ T
= 25
_
C
P
D
2.0
0.016
W
A
Derate above 25
_
C
W/
_
C
Operating and Storage
T
e
mperature Range
THERMAL CHARACTERISTICS
T , T
J
–
6
5 to +150
_
C
stg
G
A
Y
= Pb
−
Free Package
= Assembly Location
=
Y
e
ar
Characteristic
Symbol
Max
62.5
4.4
Unit
_
C/W
_
C/W
_
C
WW =
Work Week
Thermal Resistance, Junction
−
to
−
Ambient
Lead
T
e
mperature for Soldering Purposes
R
q
JA
R
q
JC
T
L
260
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Proper
strike and creepage distance must be provided.
Device
Package
Shipping
MJF47G
TO
−
220 FULLPACK
50 Units/Rail
(Pb
−
Free)
2. Measurement
made with thermocouple contacting the bottom insulated
surface (in a location beneath the die), the devices mounted on a heatsink with
thermal grease and a mounting torque of
≥
6 in. lbs.
*For additional information on our Pb
−
Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*For additional information on our Pb
−
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting
T
e
chniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
October, 2012
−
Rev. 6
MJF47/D
MJF47G
ELECTRICAL CHARACTERISTICS
(T =
25
_
C unless otherwise noted)
C
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
V
250
−
−
0.2
0.1
1
Vdc
CEO(sus)
(I =
30 mAdc, I
= 0)
C
B
Collector Cutoff Current
(V =
150 Vdc, I
= 0)
I
mAdc
mAdc
mAdc
CEO
CE
B
Collector Cutoff Current
(V =
350 Vdc, V
= 0)
I
−
CES
CE
BE
Emitter Cutoff Current
(V =
5 Vdc, I
= 0)
I
−
EBO
BE
C
DC Current Gain
h
FE
−
(I =
0.3 Adc, V
= 10 Vdc)
C
CE
30
10
150
−
(I =
1 Adc, V
= 10 Vdc)
C
CE
Collector
−
Emitter Saturation Voltage
(I =
1 Adc, I
= 0.2 Adc)
V
−
1
Vdc
Vdc
CE(sat)
C
B
Base
−
Emitter On Voltage
(I =
1 Adc, V
= 10 Vdc)
V
−
1.5
BE(on)
C
CE
DYNAMIC CHARACTERISTICS
Current Gain
−
Bandwidth Product
f
T
10
−
MHz
(I =
0.2 Adc, V
10 Vdc, f = 2 MHz)
C
CE
3. Pulse
T
e
st: Pulse Width
v
300
m
s, Duty Cycle
v
2%.
TYPICAL CHARACTERISTICS
200
100
1.4
1.2
1
V
CE
= 10 V
T =
150
°
C
J
60
40
25
°
C
V
@ I
/I =
5
C B
BE(sat)
0.8
0.6
0.4
20
10
V
BE(on)
@ V
= 4 V
CE
-ꢀ55
°
C
T =
25
°
C
J
6
4
0.2
0
V
@ I
/I =
5 V
C B
CE(sat)
2
0.02
0.04 0.06
0.1
0.2
1
2
0.02
0.04 0.06
0.1
0.2
1
2
0.4 0.6
0.4 0.6
I ,
COLLECTOR CURRENT (AMPS)
C
I ,
COLLECTOR CURRENT (AMPS)
C
Figure 1. DC Current Gain
Figure 2. “On” Voltages
2
MJF47G
1
5
T =
25
°
C
J
t
s
V
CC
I /I
= 5
= 200 V
T =
25
°
C
0.5
J
t
r
2
1
C B
V
CC
I /I
= 5
= 200 V
C B
0.2
t
d
0.5
0.1
0.05
t
f
0.2
0.1
0.02
0.01
0.05
0.02
0.05
0.1
0.2
0.5
1
2
0.02
0.05
0.1
0.2
0.5
1
2
I ,
COLLECTOR CURRENT (AMPS)
C
I ,
COLLECTOR CURRENT (AMPS)
C
Figure 3. Turn
−
On Time
Figure 4. Turn
−
Off Time
TURN-ON PULSE
V
CC
APPROX
+11 V
R
C
SCOPE
V
in
V
0
in
R
B
V
EB(off)
51
t
1
C
<< C
jd
eb
t
3
APPROX
+11 V
-ꢀ4 V
t1
≤
7 ns
100 < t
< 500
m
s
t <
15 ns
2
V
in
3
DUTY CYCLE
≈
2%
APPROX -ꢀ9 V
t
2
R
and R
VARIED TO OBTAIN
C
DESIRED CURRENT LEVELS.
B
TURN-OFF PULSE
Figure 5. Switching Time Equivalent Circuit
1
0.5
0.3
0.2
0.1
SINGLE PULSE
R
R
T
= r(t) R
q
JC
q
q
JC(t)
0.05
= 4.4
°
C/W MAX
JC
– T
= P
R
(t)
q
JC
J(pk)
C
(pk)
0.03
0.02
0.01
0.1
0.2 0.3
0.5
1
2
3
5
10
20 30
50
100
200 300
500
1K
2K 3K
5K
10 K
t, TIME (msec)
Figure 6. Thermal Response
3
MJF47G
3
2
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
−
V
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
100
m
s
500
m
s
C
CE
1
1ꢂms
0.5
dc
0.3
0.2
variable depending on conditions. Second breakdown pulse
= 150
_
C; T
is
J(pk)
C
limits are valid for duty cycles to 10% provided T
J(pk)
CURRENT LIMIT
THERMAL LIMIT @ T
= 25
°
C
0.1
v
150
°
C.
T
may be calculated from the data in
J(pk)
C
SECONDARY BREAKDOWN LIMIT
Figure 6.
At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
0.05
0.03
10
20
30
50
100
200
300
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 7. Maximum Forward Bias Safe
Operating Area
40
2
1.5
1
30
20
10
0
0.5
0
0
50
100
150
0
50
100
150
200
200
T ,
CASE TEMPERATURE (
°
C)
C
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 8. Power Derating
Figure 9. Power Derating
4
MJF47G
TEST CONDITIONS FOR ISOLATION TESTS*
MOUNTED
FULLY ISOLATED
PACKAGE
MOUNTED
FULLY ISOLATED
MOUNTED
FULLY ISOLATED
PACKAGE
PACKAGE
CLIP
CLIP
0.099″ MIN
LEADS
0.099″ MIN
LEADS
LEADS
HEATSINK
0.110″ MIN
HEATSINK
HEATSINK
Figure 10. Clip Mounting Position
for Isolation Test Number 1
Figure 11. Clip Mounting Position
for Isolation Test Number 2
Figure 12. Screw Mounting Position
for Isolation Test Number 3
*Measurement made between leads and heatsink with all leads shorted together
MOUNTING INFORMATION
4-40 SCREW
CLIP
PLAIN WASHER
HEATSINK
COMPRESSION WASHER
NUT
HEATSINK
Figure 13. Typical Mounting Techniques*
Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw
.
torque of 6 to 8 in
lbs is sufficient to provide maximum power dissipation capability.
The compression washer helps to maintain a con-
stant pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4
−
40 screw, without washers, and applying a torque in excess of 20 in
lbs will
.
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
.
Additional tests on slotted 4
−
40 screws indicate that the screw slot fails between 15 to 20 in
lbs without adversely affecting the pack-
age. However,
in order to positively ensure the package integrity of the fully isolated device, ON Semiconductor does not recommend
.
exceeding 10 in
lbs of mounting torque under any mounting conditions.
*
*
F
or more information about mounting power semiconductors see Application Note AN1040.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
220 FULLPAK
CASE 221D
−
03
ISSUE K
DATE 27 FEB 2009
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
−
T
−
PLANE
−
B
−
C
2. CONTROLLING
DIMENSION: INCH
3. 221D-01
THRU 221D-02 OBSOLETE, NEW
STANDARD 221D-03.
F
S
Q
INCHES
DIM MIN
MAX
MILLIMETERS
U
SCALE 1:1
MIN
15.67
9.96
4.50
0.60
2.95
MAX
16.12
10.63
4.90
A
B
C
D
F
0.617
0.392
0.177
0.024
0.116
0.635
0.419
0.193
0.039
0.129
A
1
2 3
1.00
3.28
H
G
H
J
0.100 BSC
2.54 BSC
−
Y
−
K
0.118
0.018
0.503
0.048
0.135
0.025
0.541
0.058
3.00
0.45
3.43
0.63
K
L
12.78
1.23
13.73
1.47
G
N
J
N
Q
R
S
U
0.200 BSC
5.08 BSC
R
0.122
0.099
0.092
0.239
0.138
0.117
0.113
0.271
3.10
2.51
2.34
6.06
3.50
2.96
2.87
6.88
L
D
3 PL
M
M
0.25 (0.010)
B
Y
MARKING
DIAGRAMS
STYLE 1:
PIN 1.
GATE
2. DRAIN
STYLE 2:
PIN 1.
BASE
STYLE 3:
PIN 1.
ANODE
2. COLLECTOR
3. EMITTER
2. CATHODE
3. ANODE
3. SOURCE
AYWW
xxxxxxG
AKA
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1.
MT 1
2. MT
2
xxxxxxG
AYWW
PIN 1.
CATHODE
2. ANODE
3. CATHODE
PIN 1.
CATHODE
2. ANODE
3. GATE
3. GATE
Bipolar
Rectifier
A
Y
WW
= Assembly Location
=
Y
e
ar
= Work Week
xxxxxx =
Specific Device Code
G
= Pb
−
Free Package
= Assembly Location
=
Y
e
ar
A
Y
xxxxxx =
Device Code
G
AKA
= Pb
−
Free Package
= Polarity Designator
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42514B
TO
−
220 FULLPAK
PAGE 1 OF 1
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