onsemi-MMDF2P02ER2
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MMDF2P02E
Power MOSFET
2 Amps, 25 Volts
P
−
Channel SO
−
8, Dual
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain
−
to
−
sourc
e
d
iode has a low reverse recovery time. These devices
are designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc
−
dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives. The avalanche energy is
specified to eliminate the guesswork in designs where inductive loads
are switched and offer additional safety margin against unexpected
voltage transients.
2 AMPERES, 25 VOLTS
R
DS(on)
= 250 m
W
P
−
Channel
D
G
Features
•
Ultra Low R
Provides Higher Efficiency and Extends Battery Life
DS(on)
S
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO
−
8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, with Soft Recovery
MARKING
DIAGRAM
8
1
F2PO2
AYWW
G
G
•
I
Specified at Elevated Temperatures
SO
−
8, Dual
CASE 751
STYLE 11
DSS
8
•
Avalanche Energy Specified
1
•
Mounting Information for SO
−
8 Package Provided
•
This is a Pb
−
Free Device
F2P02 =
Specific Device Code
J
A
Y
WW
G
= Assembly Location
=
Y
ear
Rating
Symbol
Value
25
Unit
Vdc
Vdc
Adc
= Work Week
Drain
−
to
−
Source Voltage
V
DSS
= Pb
−
Free Package
(Note: Microdot may be in either location)
Gate
−
to
−
Source Voltage
−
Continuous
V
20
GS
Drain Current
−
Continuous @ T
= 25
°
C
I
2.5
1.7
13
A
A
D
D
Drain Current
−
Continuous @ T
= 100
°
C
I
PIN ASSIGNMENT
Drain Current
−
Single Pulse (t
≤
10
m
s)
I
Apk
p
DM
T
o
tal Power Dissipation @ T
= 25
°
C
P
2.0
16
W
A
D
Source
−
1
Gate
−
1
Drain
−
1
Drain
−
1
Drain
−
2
1
2
3
4
8
7
6
5
mW/
°
C
Derate above 25
°
C
Operating and Storage
T
e
mperature Range
T , T
−
55 to 150
°
C
J
stg
Source
−
2
Single Pulse Drain
−
to
−
Source Avalanche
Energy
−
Starting T
= 25
°
C
E
mJ
AS
Gate
−
2
Drain
−
2
245
J
T
o
p View
(V =
20 Vdc, V
= 10 Vdc, Peak
DD
GS
I =
7.0 Apk, L = 10 mH, R
= 25
W
)
L
G
ORDERING INFORMATION
Thermal Resistance, Junction
−
to
−
Ambient
R
62.5
260
°
C/W
°
C
q
JA
†
Device
Package
Shipping
Maximum Lead
T
e
mperature for Soldering
Purposes, 0.0625
″
from case for 10 sec.
T
L
MMDF2P02ER2G
SO
−
8
(Pb
−
Free)
2500
T
a
pe & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative
sign for P
−
Channel device omitted for clarity.
2. Mounted
on 2
″
square FR4 board (1
″
sq. 2 oz. Cu 0.06
″
thick single sided) with
one die operating, 10 sec. max.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011
−
Rev. 9
MMDF2P02E/D
MMDF2P02E
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
(V =
0 Vdc, I
= 250
m
Adc)
V
Vdc
(BR)DSS
25
−
−
−
GS
D
T
e
mperature Coefficient (Positive)
−
2.2
mV/
°
C
m
Adc
Zero Gate Voltage Drain Current
I
DSS
GSS
(V =
20 Vdc, V
= 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V =
20 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate
−
Body Leakage Current (V
=
20 Vdc, V
= 0)
I
−
−
100
nAdc
Vdc
GS
DS
Gate Threshold Voltage
V
GS(th)
DS(on)
(V =
V ,
I =
250
m
Adc)
1.0
−
2.0
3.8
3.0
−
DS
GS
D
T
e
mperature Coefficient (Negative)
Static Drain
−
to
−
Source On
−
Resistance
R
W
(V =
10 Vdc, I
= 2.0 Adc)
−
−
0.19
0.3
0.25
0.4
GS
D
(V =
4.5 Vdc, I
= 1.0 Adc)
GS
D
Forward Transconductance (V
= 3.0 Vdc, I
= 1.0 Adc)
g
FS
1.0
2.8
−
Mhos
pF
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
D
C
iss
−
−
−
340
220
75
475
300
150
(V =
16 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
rss
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
−
−
−
−
−
20
40
53
41
13
29
30
28
10
1.0
3.5
3.0
40
80
106
82
26
58
60
56
15
−
ns
d(on)
Rise Time
t
r
(V =
10 Vdc, I
= 2.0 Adc,
DD
GS
D
V
= 5.0 Vdc, R
= 6.0
W
)
G
Turn
−
Off Delay Time
Fall Time
t
t
t
d(off)
t
f
Turn
−
On Delay Time
Rise Time
d(on)
t
r
(V =
10 Vdc, I
= 2.0 Adc,
DD
GS
D
G
V
= 10 Vdc, R
= 6.0
W
)
Turn
−
Off Delay Time
Fall Time
d(off)
t
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
nC
(V =
16 Vdc, I
= 2.0 Adc,
DS
D
V
= 10 Vdc)
GS
−
−
SOURCE
−
DRAIN DIODE CHARACTERISTICS
(I =
2.0 Adc, V
= 0 Vdc)
V
SD
−
−
−
−
−
1.5
32
2.0
64
−
Vdc
ns
S
GS
Reverse Recovery Time
See Figure 11
t
rr
t
a
19
(I =
2.0 Adc, V
= 0 Vdc,
S
GS
dI /dt
= 100 A/
m
s)
S
t
b
12
−
Reverse Recovery Storage Charge
Q
0.035
−
m
C
RR
3. Negative
sign for P
−
Channel device omitted for clarity.
4. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
5. Switching
characteristics are independent of operating junction temperature.
2
MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4
3
2
1
0
4
V
≥
10 V
5 V
V
= 10
7 V
DS
T = 25
°
C
GS
J
4.7 V
4.5 V
3
2
1
0
4.3 V
4.1 V
100
°
C
25
°
C
3.9 V
3.7 V
T =
-55
°
C
J
3.5 V
3.3 V
0
0.4
0.8
1.2
1.6
2
2.5
3
3.5
4
4.5
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V ,
GATE-TO-SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.6
0.5
0.4
0.6
T = 25
°
C
J
I =
1 A
D
T =
25
°
C
J
0.5
0.4
0.3
0.2
0.1
0.3
0.2
0.1
0
V
= 4.5
GS
10 V
1
3
4
5
6
7
8
10
9
0
0.5
1.5
2
V
, GATE-TO-SOURCE VOLTAGE (VOLTS)
I ,
DRAIN CURRENT (AMPS)
D
GS
Figure 3. On
−
Resistance versus
Gate
−
to
−
Source Voltage
Figure 4. On
−
Resistance versus Drain Current
and Gate Voltage
2.0
100
V =
10 V
GS
I =
2 A
V
= 0 V
GS
D
1.5
1.0
0.5
0
T =
125
°
C
J
10
100
°
C
1
-ꢀ50
-ꢀ25
0
25
50
75
100
125
150
0
4
8
12
16
20
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
Figure 6. Drain
−
to
−
Source Leakage Current
Figure 5. On
−
Resistance Variation with
versus Voltage
Temperature
3
MMDF2P02E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
During the turn
−
on and turn
−
off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
t
t
= R
C In
[V /(V
−
V )]
G iss
GG GG
GSP
d(on)
d(off)
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
= R
C In
(V /V
)
GG GSP
G
iss
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off
−
state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
average input current (I
) can be made from a
G(
A
V
)
on
−
state when calculating t
.
d(off)
rudimentary analysis of the drive circuit so that
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
known as the plateau voltage, V
. Therefore,
rise and fall
GS
SGP
times may be approximated by the following:
t =
Q x
R /(V
−
V )
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
1000
12
16
12
8
V
= 0 V
V
= 0 V
GS
T = 25
°
C
DS
J
QT
C
iss
800
600
400
9
6
V
GS
V
DS
Q1
Q2
C
C
C
rss
iss
oss
rss
3
0
4
0
Q3
200
0
I =
2 A
D
C
T =
25
°
C
J
10
5
0
5
10
15
20
25
30
0
2
4
6
8
Q ,
TOTAL GATE CHARGE (nC)
10
12
V
V
DS
GS
g
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage versus Total Charge
Figure 7. Capacitance Variation
4
MMDF2P02E
100
2
V
I =
2 A
= 10 V
T =
25
°
C
J
VGS = 0 V
DD
D
V
= 10 V
1.6
1.2
GS
T =
25
°
C
J
t
0.8
0.4
0
d(off)
t
r
t
f
t
d(on)
10
1
10
R ,
GATE RESISTANCE (OHMS)
100
0.6
0.8
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
SD
1
1.2
1.4
1.6
V
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage
versus Current
di/dt = 300 A/
m
s
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
This MOSFET can be safely used in switching circuits
with unclamped inductive loads. For reliable operation, the
stored energy from circuit inductance dissipated in the
transistor while in avalanche must be less than the rated limit
and must be adjusted for operating conditions differing from
those specified. Although industry practice is to rate in terms
of energy, avalanche energy capability is not a constant. The
energy rating decreases non
−
linearly with an increase of
peak current in avalanche and peak junction temperature.
Although many MOSFETs can withstand the stress of
drain
−
to
−
source avalanche at currents up to rated pulsed
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
(I )
nor rated voltage (V
) is exceeded, and that the
current (I
), the energy rating is specified at rated
DM
DSS
DM
transition time (t , t ) does not exceed 10
m
s. In addition the
continuous current (I ), in accordance with industry
r
f
D
total power averaged over a complete switching cycle must
not exceed (T
−
T )/(R
).
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
J(MAX)
C
q
JC
energy at currents below rated continuous I
can safely be
D
assumed to equal the values indicated.
5
MMDF2P02E
280
100
10
Mounted on 2
″
sq. FR4 board (1
″
sq. 2 oz. Cu 0.06
″
thick single sided) with one die operating, 10s max.
V
= 20 V
SINGLE PULSE
I pk = 7 A
GS
240
200
160
120
80
T =
25
°
C
C
10
m
s
100
m
s
10 ms
1
dc
0.1
R
LIMIT
DS(on)
40
0
THERMAL LIMIT
PACKAGE LIMIT
0.01
25
50
75
100
125
150
0.1
1
10
100
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.1
Normalized to
q
ja at 10s.
0.05
0.02
Chip
0.0175
W
0.0710
W
0.2706
W
0.5776
W
0.7086
W
0.01
0.01
0.0154 F
0.0854 F
1.0E+00
0.3074 F
1.7891 F
107.55 F
SINGLE PULSE
1.0E-04
Ambient
1.0E+03
0.001
1.0E-05
1.0E-03
1.0E-02
1.0E-01
t, TIME (s)
1.0E+01
1.0E+02
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 15. Diode Reverse Recovery Waveform
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−
X
−
A
4. MAXIMUM
MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION
D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751
−
01 THRU 751
−
06 ARE OBSOLETE. NEW
STANDARD IS 751
−
07.
S
M
M
Y
B
0.25 (0.010)
1
K
−
Y
−
MILLIMETERS
DIM MIN
MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N
X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−
Z
−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb
−
Free)
IC
IC
(Pb
−
Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
=
Y
e
ar
Y
Y
W
G
=
Y
e
ar
= Work Week
= Pb
−
Free Package
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC
−
8 NB
PAGE 1 OF 2
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and
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
or its subsidiaries in the United States and/or other countries.
onsemi
reserves
the right to make changes without further notice to any products herein.
onsemi
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purpose, nor does
onsemi
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special, consequential or incidental damages.
onsemi
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©
Semiconductor Components Industries, LLC, 2019
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1.
EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1.
COLLECTOR, DIE, #1
2. COLLECTOR,
#1
3. COLLECTOR,
#2
4. COLLECTOR,
#2
5. BASE,
#2
PIN 1.
DRAIN, DIE #1
2. DRAIN,
#1
3. DRAIN,
#2
4. DRAIN,
#2
5. GATE,
#2
PIN 1.
ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER,
#2
7. BASE,
#1
6. SOURCE,
#2
7. GATE,
#1
7. BASE
8. EMITTER
8. EMITTER,
#1
8. SOURCE,
#1
8. COMMON
CATHODE
STYLE 5:
STYLE 6:
PIN 1.
SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1.
COLLECTOR, DIE #1
2. BASE,
#1
PIN 1.
DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1.
INPUT
2. EXTERNAL
BYPASS
3. THIRD
STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE
3
7. SECOND
STAGE Vd
8. FIRST
STAGE Vd
3. DRAIN
3. BASE,
#2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR,
#2
5. COLLECTOR,
#2
6. EMITTER,
#2
7. EMITTER,
#1
8. COLLECTOR,
#1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1.
GROUND
2. BIAS
1
STYLE 11:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 12:
PIN 1.
EMITTER, COMMON
2. COLLECTOR,
DIE #1
3. COLLECTOR,
DIE #2
4. EMITTER,
COMMON
5. EMITTER,
COMMON
6. BASE,
DIE #2
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS
2
7. INPUT
8. GROUND
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. DRAIN
2
7. DRAIN
1
8. DRAIN
1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE,
DIE #1
8. EMITTER,
COMMON
STYLE 13:
PIN 1.
N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1.
N
−
SOURCE
2. N
−
GATE
STYLE 15:
PIN 1.
ANODE 1
2. ANODE
1
STYLE 16:
PIN 1.
EMITTER, DIE #1
2. BASE,
DIE #1
3. P
−
SOURCE
4. P
−
GATE
5. P
−
DRAIN
6. P
−
DRAIN
7. N
−
DRAIN
8. N
−
DRAIN
3. ANODE
1
4. ANODE
1
5. CATHODE,
COMMON
6. CATHODE,
COMMON
7. CATHODE,
COMMON
8. CATHODE,
COMMON
3. EMITTER,
DIE #2
4. BASE,
DIE #2
5. COLLECTOR,
DIE #2
6. COLLECTOR,
DIE #2
7. COLLECTOR,
DIE #1
8. COLLECTOR,
DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1.
VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 20:
PIN 1.
ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1.
SOURCE (N)
2. GATE
(N)
3. SOURCE
(P)
4. GATE
(P)
5. DRAIN
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. MIRROR
2
7. DRAIN
1
8. MIRROR
1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1.
CATHODE 1
2. CATHODE
2
3. CATHODE
3
4. CATHODE
4
5. CATHODE
5
6. COMMON
ANODE
7. COMMON
ANODE
8. CATHODE
6
PIN 1.
I/O LINE 1
PIN 1.
LINE 1 IN
PIN 1.
BASE
2. COMMON
CATHODE/VCC
3. COMMON
CATHODE/VCC
4. I/O
LINE 3
5. COMMON
ANODE/GND
6. I/O
LINE 4
7. I/O
LINE 5
8. COMMON
ANODE/GND
2. COMMON
ANODE/GND
3. COMMON
ANODE/GND
4. LINE
2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE
2 OUT
6. COMMON
ANODE/GND
7. COMMON
ANODE/GND
8. LINE
1 OUT
STYLE 25:
PIN 1.
VIN
2. N/C
STYLE 26:
PIN 1.
GND
2. dv/dt
STYLE 27:
PIN 1.
ILIMIT
2. OVLO
STYLE 28:
PIN 1.
SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1.
DRAIN 1
2. DRAIN
1
STYLE 29:
PIN 1.
BASE, DIE #1
2. EMITTER,
#1
3. BASE,
#2
3. GATE
2
4. SOURCE
2
5. SOURCE
1/DRAIN 2
6. SOURCE
1/DRAIN 2
7. SOURCE
1/DRAIN 2
8. GATE
1
4. EMITTER,
#2
5. COLLECTOR,
#2
6. COLLECTOR,
#2
7. COLLECTOR,
#1
8. COLLECTOR,
#1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
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DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC
−
8 NB
PAGE 2 OF 2
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