onsemi-MMSF3P02HDR2G
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MMSF3P02HD
Power MOSFET
3 Amps, 20 Volts
P
−
Channel SO
−
8
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain
−
to
−
source diode has a very low reverse recovery time. These
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc
−
dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
3 AMPERES, 20 VOLTS
R
DS(on)
= 75 m
W
P
−
Channel
D
G
Features
S
•
Ultra Low R
Provides Higher Efficiency and Extends Battery Life
DS(on)
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO
−
8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
MARKING
DIAGRAM
8
1
SO
−
8
CASE 751
STYLE 13
S3P02
AYWW
G
G
8
•
I
Specified at Elevated Temperature
•
Avalanche Energy Specified
DSS
1
•
Mounting Information for SO
−
8 Package Provided
•
This is a Pb
−
Free Device
S3P02 =
Device Code
A
Y
WW
G
= Assembly Location
=
Y
ear
J
= Work Week
Rating
Symbol
Value
20
Unit
Vdc
Vdc
Vdc
Adc
= Pb
−
Free Package
(Note: Microdot may be in either location)
Drain
−
to
−
Source Voltage
V
DSS
Drain
−
to
−
Gate Voltage (R
= 1.0 M
W
)
V
20
GS
DGR
PIN ASSIGNMENT
Gate
−
to
−
Source Voltage
−
Continuous
V
20
GS
Drain Current
−
Continuous @ T
= 25
°
C
I
5.6
3.6
30
A
A
D
D
N
−
C
Source
Source
Drain
Drain
Drain
1
2
3
4
8
7
6
5
Drain Current
−
Continuous @ T
= 100
°
C
I
Drain Current
−
Single Pulse (t
≤
10
m
s)
I
Apk
W
p
DM
P
2.5
−
55 to 150
567
A
D
Operating and Storage
T
e
mperature Range
T , T
°
C
Gate
Drain
J
stg
Single Pulse Drain
−
to
−
Source Avalanche
E
mJ
AS
Energy
−
Starting T
= 25
°
C (V
= 20 Vdc,
J
DD
ORDERING INFORMATION
V
= 5.0 Vdc, Peak I
= 9.0
Apk, L = 14
L
G
GS
mH, R
= 25
W
)
†
Device
Package
Shipping
Thermal Resistance, Junction
−
to
−
Ambient
R
q
50
°
C/
W
JA
MMSF3P02HDR2G
SO
−
8
(Pb
−
Free)
2500
T
a
pe & Reel
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8
″
from case for 10 seconds
T
L
260
°
C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative
sign for P
−
Channel device omitted for clarity.
2. Mounted
on 2
″
square FR4 board (1
″
sq. 2 oz. Cu 0.06
″
thick single sided),
10 sec. max.
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011
−
Rev. 8
MMSF3P02HD/D
MMSF3P02HD
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
(V =
0 Vdc, I
= 250
m
Adc)
V
Vdc
(BR)DSS
20
−
−
−
GS
D
T
e
mperature Coefficient (Positive)
−
24
mV/
°
C
m
Adc
Zero Gate Voltage Drain Current
I
DSS
GSS
(V =
20 Vdc, V
= 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V =
20 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate
−
Body Leakage Current (V
=
20 Vdc, V
= 0)
I
−
−
100
nAdc
Vdc
GS
DS
Gate Threshold Voltage
V
GS(th)
DS(on)
(V =
V ,
I =
250
m
Adc)
1.0
−
1.5
4.0
2.0
−
DS
GS
D
T
e
mperature Coefficient (Negative)
mV/
°
C
Static Drain
−
Source On
−
Resistance
R
W
(V =
10 Vdc, I
= 3.0 Adc)
−
−
0.06
0.08
0.075
0.095
GS
D
(V =
4.5 Vdc, I
= 1.5 Adc)
GS
D
Forward Transconductance (V
= 3.0 Vdc, I
= 1.5 Adc)
g
FS
3.0
7.2
−
mhos
pF
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
D
C
iss
−
−
−
1010
740
1400
920
(V =
16 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
rss
260
490
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
−
−
−
−
−
25
135
54
50
270
108
168
32
ns
d(on)
Rise Time
t
r
(V =
10 Vdc, I
= 3.0 Adc,
DD
GS
D
V
= 4.5 Vdc, R
= 6.0
W
)
G
Turn
−
Off Delay Time
Fall Time
t
t
t
d(off)
t
f
84
Turn
−
On Delay Time
Rise Time
16
d(on)
t
r
40
80
(V =
10 Vdc, I
= 3.0 Adc,
DD
GS
D
G
V
= 10 Vdc, R
= 6.0
W
)
Turn
−
Off Delay Time
Fall Time
110
97
220
194
46
d(off)
t
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
33
nC
3.0
11
−
(V =
16 Vdc, I
= 3.0 Adc,
DS
D
V
= 10 Vdc)
GS
−
10
−
SOURCE
−
DRAIN DIODE CHARACTERISTICS
V
Vdc
ns
SD
(I =
3.0 Adc, V
= 0 Vdc)
S
GS
−
−
1.35
0.96
1.75
(I =
3.0 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
−
Reverse Recovery Time
t
−
−
−
−
76
32
−
−
−
−
rr
t
a
(I =
3.0 Adc, V
= 0 Vdc,
S
GS
dI /dt
= 100 A/
m
s)
S
t
44
b
Reverse Recovery Stored Charge
Q
0.133
m
C
RR
3. Negative
sign for P
−
Channel device omitted for clarity.
4. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
5. Switching
characteristics are independent of operating junction temperature.
2
MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
6
5
6
3.5 V
V
= 10 V
GS
3.3 V
T = 25
°
C
V
≥
10 V
J
DS
5
4
3
2
1
3.7 V
3.9 V
4.5 V
3.1 V
2.9 V
4
3
2
1
0
T =
100
°
C
J
2.7 V
2.5 V
25
°
C
–
5
5
°
C
2.6
0
1.6
0
0.2 0.4
0.6
0.8
1
1.2 1.4
1.6 1.8
2
1.8
2
2.2
2.4
2.8
3
3.2
3.4
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V ,
GATE-TO-SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.6
0.4
0.09
0.08
T = 25
°
C
J
I
= 1.5 A
D
T = 25
°
C
J
V
= 4.5 V
GS
0.07
0.2
10 V
0.06
0.05
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
V
, GATE-TO-SOURCE VOLTAGE (VOLTS)
I ,
DRAIN CURRENT (AMPS)
D
GS
Figure 3. On
−
Resistance versus
Gate
−
T
o
−
Source Voltage
Figure 4. On
−
Resistance versus Drain Current
and Gate Voltage
1.20
1000
V
= 0 V
V
= 10 V
= 3.0 A
GS
GS
I
D
1.10
1.00
T =
125
°
C
J
100
0.90
0.80
10
-ꢀ50
0
25
50
75
100
125
150
0
4
8
12
16
20
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
To
−
Source Leakage
Temperature
Current versus Voltage
3
MMSF3P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off
−
state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on
−
state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
−
V )
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn
−
on and turn
−
off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
−
V )]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
G
iss
GG GSP
3500
12
24
20
T =
25
°
C
J
V
= 0 V
V
= 0 V
GS
DS
QT
3000
2500
2000
10
8
C
V
GS
iss
16
12
8
6
I
D
= 3 A
1500
1000
T =
25
°
C
J
Q1
Q2
C
C
iss
rss
4
2
0
C
oss
4
500
0
C
rss
V
DS
Q3
0
10
5
0
5
10
15
20
0
4
8
12
16
20
24
28
32
36
V
V
DS
GS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)
Q , TOTAL CHARGE (nC)
T
Figure 7. Capacitance Variation
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
Voltage versus Total Charge
4
MMSF3P02HD
1000
100
10
V
= 10 V
DD
GS
I
D
= 3 A
V
= 10 V
T =
25
°
C
J
t
d(off)
t
f
t
r
t
d(on)
1
10
100
R ,
GATE RESISTANCE (OHMS)
G
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN
−
TO
−
SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
3
di/dt = 300 A/
m
s
Standard Cell Density
V
= 0 V
GS
t
T =
25
°
C
J
rr
2.5
2
High Cell Density
t
rr
t
b
t
a
1.5
1
0.5
0
0.3 0.4
0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
1.4
t, TIME
V
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
Figure 11. Reverse Recovery Time (t
rr
)
5
MMSF3P02HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non
−
linearly with an increase of peak current in avalanche
and peak junction temperature.
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Although many E
−
FETs can withstand the stress of
drain
−
to
−
source avalanche at currents up to rated pulsed
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded, and that the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t , t ) does not exceed 10
m
s. In addition the
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
r
f
total power averaged over a complete switching cycle must
not exceed (T
−
T )/(R
).
energy at currents below rated continuous I
can safely be
D
J(MAX)
C
q
JC
assumed to equal the values indicated.
A power MOSFET designated E
−
FET can be safely used
in switching circuits with unclamped inductive loads. For
600
100
I
D
= 9 A
V
= 20 V
GS
SINGLE PULSE
= 25
°
C
100
m
s
T
C
1 ms
10
1
450
300
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
150
0
0.1
Mounted on 2
″
sq. FR4 board (1
″
sq. 2 oz. Cu 0.06
″
thick single sided), 10s max.
0.01
25
50
75
100
125
150
0.1
1
10
100
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6
MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.1
Normalized to
q
ja at 10s.
0.05
0.02
0.01
Chip
0.0163
W
0.0652
W
0.1988
W
0.6411
W
0.9502
W
0.01
0.0307 F
0.1668 F
1.0E+00
0.5541 F
1.9437 F
72.416 F
Ambient
1.0E+03
SINGLE PULSE
1.0E-04
0.001
1.0E-05
1.0E-03
1.0E-02
1.0E-01
t, TIME (s)
1.0E+01
1.0E+02
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 15. Diode Reverse Recovery Waveform
7
MMSF3P02HD
PACKAGE DIMENSIONS
SOIC
−
8
CASE 751
−
07
ISSUE AG
NOTES:
−
X
−
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM
MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION
D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751
−
01 THRU 751
−
06 ARE OBSOLETE. NEW
STANDARD IS 751
−
07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−
Y
−
G
MILLIMETERS
DIM MIN
MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N
X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−
Z
−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
STYLE 13:
PIN 1.
N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
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