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SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
N–Channel Enhancement–Mode Silicon Gate
15 AMPERES
60 VOLTS
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFE
T
s
. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
R
= 0.12 OHM
DS(on)
TM
D
New Features of TMOS V
G
•
On–resistance Area Product about One–half that of Standard
MOSFE
T
s
w
ith New Low Voltage, Low R
T
e
chnology
DS(on)
Faster Switching than E–FET Predecessors
CASE 418B–02, Style 2
S
2
•
D PAK
Features Common to TMOS V and TMOS E–FETs
•
•
•
•
Avalanche Energy Specified
and V
Specified at Elevated
T
e
mperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit
T
a
pe & Reel,
Add T4 Suffix to Part Number
I
DSS
DS(on)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
Rating
Symbol
Value
60
Unit
Drain–Source Voltage
V
DSS
Vdc
Vdc
Drain–Gate Voltage (R
= 1.0 M
Ω
)
V
DGR
60
GS
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Non–Repetitive (t
≤
10 ms)
V
±
20
±
25
Vdc
Vpk
GS
V
GSM
p
Drain Current — Continuous @ 25
°
C
Drain Current
— Continuous @ 100
°
C
I
I
15
8.7
45
Adc
D
D
Drain Current
— Single Pulse (t
≤
10
µ
s)
I
Apk
p
DM
T
o
tal Power Dissipation @ 25
°
C
Derate above 25
°
C
P
D
55
0.37
3.0
Watts
W/
°
C
Watts
T
o
tal Power Dissipation @ T
= 25
°
C (1)
A
Operating and Storage
T
e
mperature Range
T ,
T
stg
– 55 to 175
113
°
C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T
= 25
°
C
E
AS
mJ
J
(V
DD
= 25 Vdc, V
= 10 Vdc, I
= 15 Apk, L = 1.0 mH, R
= 25
Ω
)
GS L
G
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
R
R
R
2.73
62.5
50
°
C/W
°
C
θ
JC
θ
JA
θ
JA
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8
″
from case for 10 seconds
T
260
L
(1) When
surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown
V
o
ltage
V
(BR)DSS
(V
GS
= 0 Vdc, I
= 0.25 mAdc)
60
—
—
67
—
—
Vdc
mV/
°
C
D
T
e
mperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
µ
Adc
DSS
(V
DS
(V
DS
= 60 Vdc, V
= 60 Vdc, V
= 0 Vdc)
= 0 Vdc, T
= 150
°
C)
—
—
—
—
10
100
GS
GS
J
Gate–Body Leakage Current (V
=
±
20 Vdc, V
DS
= 0)
I
—
—
100
nAdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V
DS
= V
, I
= 250
µ
Adc)
2.0
—
2.7
5.0
4.0
—
Vdc
mV/
°
C
GS
D
T
e
mperature Coefficient (Negative)
Static Drain–Source On–Resistance (V
= 10 Vdc, I
= 7.5 Adc)
R
V
—
0.08
0.12
Ohm
Vdc
GS
D
DS(on)
Drain–Source On–Voltage (V
GS
= 10 Vdc)
DS(on)
(I =
15 Adc)
—
—
2.0
—
2.2
1.9
D
(I =
7.5 Adc, T
= 150
°
C)
D
J
Forward Transconductance (V
DS
= 8.0 Vdc, I
= 7.5 Adc)
g
4.0
6.2
—
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
469
148
35
660
200
60
iss
(V
DS
= 25 Vdc, V
= 0 Vdc,
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
7.6
51
20
100
40
70
20
—
ns
d(on)
(V
= 30 Vdc, I
= 15 Adc,
D
Rise Time
DD
DS
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
18
d(off)
R
= 9.1
Ω
)
t
f
33
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
14.4
2.8
6.4
6.1
nC
(V
= 48 Vdc, I
= 15 Adc,
D
V
GS
= 10 Vdc)
—
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
V
Vdc
ns
SD
(I =
15 Adc, V
(I =
15 Adc, V
GS
= 0 Vdc)
= 0 Vdc, T
= 150
°
C)
S
GS
—
—
1.05
0.9
1.6
—
S
J
Reverse Recovery Time
(See Figure 14)
t
—
—
—
—
59.3
46
—
—
—
—
rr
t
a
(I =
15 Adc, V
= 0 Vdc,
dI /dt
= 100 A/
µ
s)
S
GS
S
t
13.3
0.165
b
Reverse Recovery Stored Charge
Q
µ
C
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″
from package to center of die)
L
—
—
4.5
7.5
—
—
nH
nH
D
Internal Source Inductance
(Measured from the source lead 0.25
″
from package to source bond pad)
L
S
(1) Pulse
T
e
st: Pulse Width
≤
300
µ
s, Duty Cycle
≤
2%.
(2) Switching
characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
30
25
30
V
= 10 V
GS
9 V
T
= 25
°
C
V
≥
10 V
J
DS
8 V
25
20
15
10
7 V
100
°
C
20
15
10
25
°
C
T
=
–
5
5
°
C
J
6 V
5 V
5
0
5
0
0
1
2
3
4
5
6
7
2
4
6
8
10
V
, DRAIN–TO–SOURCE VO
L
TAGE (VOLTS)
V ,
GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.2
0.13
0.11
0.09
V
= 10 V
T
= 25
°
C
GS
J
0.14
T
= 100
°
C
J
V
= 10 V
GS
25
°
C
0.08
0.02
15 V
0.07
0.05
–
5
5
°
C
0
5
10
15
20
25
30
0
5
10
I ,
DRAIN CURRENT (AMPS)
D
15
20
25
30
I
, DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
100
2
V
= 0 V
GS
V
= 10 V
GS
= 7.5 A
I
D
1.6
1.2
T
= 125
°
C
J
0.8
0.4
10
–
5
0
–
2
5
0
25
50
75
100
125
C)
150
175
0
10
20
30
40
50
60
T ,
JUNCTION TEMPER
A
T
URE (
°
V
DS
, DRAIN–TO–SOURCE VO
L
TAGE (VOLTS)
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
∆
t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFE
T
s
h
ave finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequentl
y
,
i
s not specified.
The resistive switching time variation versus gate resis-
tance (Figure
9) shows how typical switching performance is
affected by the parasitic circuit elements.
If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed.
The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components.
Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load.
Power MOSFE
T
s
m
ay be safely
operated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In
most cases, a satisfactory estimate of average input
current (I
the drive circuit so that
) can be made from a rudimentary analysis of
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V
remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore,
rise and fall times may
SGP
be approximated by the following:
t =
Q x
R /(V
– V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
= the gate drive resistance
GG
GG
R
G
and Q
and V
GSP
are read from the gate charge curve.
2
During the turn–on and turn–off delay times, gate current is
not constant.
The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
1500
1200
V
= 0 V
V
= 0 V
T
= 25
°
C
DS
GS
J
C
iss
900
C
rss
600
300
0
C
iss
C
oss
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
12
10
60
50
1000
100
V
= 30 V
= 15 A
= 10 V
= 25
°
C
DD
QT
I
V
T
D
GS
V
GS
J
8
6
4
40
30
20
t
r
Q1
Q2
t
f
t
t
d(off)
I
T
= 15 A
= 25
°
C
D
J
10
1
d(on)
2
0
10
0
V
Q3
3
DS
12
0
6
9
15
1
10
, GATE RESISTANCE (OHMS)
G
100
Q ,
TOTAL CHARGE (nC)
R
T
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
15
V
= 0 V
GS
= 25
°
C
T
J
12
9
6
3
0
0.5
0.7
0.9
1.1
1.3
1.5
V
, SOURCE–TO–DRAIN VO
L
TAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FE
T
s
c
an withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V
) is exceeded and the transition
DM
DSS
continuous current (I
), in accordance with industry custom.
D
time (t ,t ) do not exceed 10
µ
s. In addition the total power
averaged over a complete switching cycle must not exceed
r f
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
(T
– T
)/(R ).
J(MAX)
C
θ
JC
currents below rated continuous I
can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
120
100
100
10
V
= 10 V
GS
SINGLE PULSE
= 25
C
I
= 15 A
D
T
°
C
10
µ
s
80
60
40
100
µ
s
1 ms
10 ms
1.0
0.1
dc
R
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
DS(on)
20
0
0.1
1.0
10
100
25
50
75
100
125
150
C)
175
T ,
STARTING JUNCTION TEMPER
A
T
URE (
°
V
, DRAIN–TO–SOURCE VO
L
TAGE (VOLTS)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P
0.05
(pk)
0.1
R
(t) = r(t) R
JC
θ
JC
θ
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
0.01
SINGLE PULSE
t
READ TIME AT t
T
1
1
t
– T
= P
R (t)
(pk)
θ
JC
2
J(pk)
C
DUTY CYCLE, D = t
/t
1 2
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
3
R
= 50
°
C/W
θ
JA
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size
≈
450 mils x 350 mils
2.5
2.0
1.5
1
di/dt
I
S
t
rr
t
t
a
b
TIME
0.5
0.25 I
t
S
p
0
25
50
75
100
125
150
175
I
S
T ,
AMBIENT TEMPER
A
T
URE (
°
C)
A
2
Figure 15. D
PAK Power Derating Curve
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
2
INFORMATION FOR USING THE D
PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLIC
A
T
IONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.33
8.38
0.08
2.032
0.42
0.24
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
function of the drain pad size.
These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
junction temperature of the die, R
θ
JA
, the maximum rated
, the thermal resistance
R
versus drain pad area is shown in Figure 16.
J(max)
θ
JA
70
from the device junction to ambient, and the operating
temperature, T
. Using the values provided on the data sheet,
Board Material = 0.0625
″
A
G–10/FR–4, 2 oz Copper
T
= 25
°
C
A
P
can be calculated as follows:
D
60
50
2.5 Watts
3.5 Watts
T
– T
A
J(max)
P
=
D
R
θ
JA
40
30
20
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T
of 25
°
C, one can
5 Watts
A
2
calculate the power dissipation of the device. For a D
PAK
device, P
is calculated as follows.
D
0
2
4
6
8
10
12
14
16
A, AREA (SQUARE INCHES)
175
°
C – 25
°
C
= 3.0
Watts
P
=
D
Figure 16. Thermal Resistance versus Drain Pad
50
°
C/W
2
Area for the D
PAK Package (Typical)
2
Th
e
5
0
°
C/
W
f
o
r
t
h
e
D
P
A
K
p
ackag
e
a
ssume
s
t
h
e
u
s
e
o
f
t
he
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 3.0 Watts. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC–59,
SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223,
SO–8, SO–14, SO–16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.
SOLDER PASTE
OPENINGS
2
registration. This is not the case with the DPAK and D
PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or “tombstoning” may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
STENCIL
Figure 17. Typical Stencil for DPAK and
2
D PAK
Packages
2
Figure 17 shows a typical stencil for the DPAK and D
PAK
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•
When shifting from preheating to soldering, the maximum
temperature gradient shall be 5
°
C or less.
•
After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•
Always preheat the device.
•
The delta temperature between the preheat and soldering
should be 100
°
C or less.*
•
Mechanical stress or shock should not be applied during
cooling.
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10
°
C.
* Soldering
a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due
to shadowing and the inability to set the wave height to
2
•
The soldering temperature and time shall not exceed
260
°
C for more than 10 seconds.
incorporate other surface mount components, the D
PAK is
not recommended for wave soldering.
8
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HE
A
T
ING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 17
7
–
189
°
C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed.
T
a
ken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typ
e
o
f
s
olde
r
u
sed, an
d
t
h
e
t
yp
e
o
f
b
oar
d
o
r
s
ubstrat
e
m
aterial
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES
2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
ZONES 4 & 7
“SOAK”
STEP 5
HEATING
STEP 6
VENT
STEP 7
COOLING
205
PEAK AT
SOLDER JOINT
°
TO 219
°
C
“SPIKE”
170
°
C
200
150
100
50
°
C
°
C
°
C
°
C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160
°
C
150
°
C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100
°
C
140
°
C
MASS OF ASSEMB
L
Y
)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 18. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
PACKAGE DIMENSIONS
C
E
V
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
4
Y14.5M, 1982.
2. CONTROLLING
DIMENSION: INCH.
INCHES
MILLIMETERS
STYLE 2:
PIN 1.
GATE
A
DIM
A
B
C
D
E
MIN
MAX
0.380
0.405
0.190
0.035
0.055
MIN
8.64
9.65
4.06
0.51
1.14
MAX
9.65
10.29
4.83
0.89
1.40
S
0.340
0.380
0.160
0.020
0.045
2. DRAIN
3. SOURCE
4. DRAIN
1
2
3
–T–
SEATING
PLANE
K
G
H
J
K
S
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.575
0.045
0.110
0.025
0.110
0.625
0.055
2.03
0.46
2.79
0.64
J
G
2.29
2.79
H
14.60
1.14
15.88
1.40
D
3 PL
V
M
0.13 (0.005)
T
CASE 418B–02
ISSUE B
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r
eserves the right to make changes without further notice to any products herein.
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o
r
g
uarante
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egarding
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