onsemi-MTD20P06HDL
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MTD20P06HDL
Preferred Device
Power MOSFET
20 Amps, 60 Volts, Logic
Level
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low−voltage, high−speed switching applications in power supplies,
converters and PWM motor controls, and other inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional
safety margin against unexpected voltage transients.
20 AMPERES, 60 VOLTS
R
DS(on)
= 175 m
W
P−Channel
D
Features
•
Ultra Low R
, High−Cell Density, HDTMOS
DS(on)
•
Diode is Characterized for Use in Bridge Circuits
and V
Specified at Elevated Temperature
G
•
I
DSS
DS(on)
•
Avalanche Energy Specified
•
Pb−Free Package is Available
S
MARKING DIAGRAM & PIN ASSIGNMENTS
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
Rating
Drain−Source Voltage
Symbol
Value
60
Unit
Vdc
Vdc
Gate 1
4
V
DSS
DGR
YWW
4
Drain−Gate Voltage (R
= 1.0 M
W
)
V
V
60
GS
Drain 2
20P
Drain
2
1
06HLG
Gate−Source Voltage
− Continuous
3
DPAK
CASE 369C
V
“
15
“
20
Vdc
Vpk
GS
Source 3
− Non−Repetitive (t
v
10 ms)
p
GSM
(Surface Mount)
STYLE 2
Drain Current
− Continuous
− Continuous @ 100
°
C
− Single Pulse (t
v
10
m
s)
I
I
15
9.0
45
Adc
Apk
D
D
I
p
DM
20P06HL =
Device Code
T
o
tal Power Dissipation
Derate above 25
°
C
P
72
0.58
1.75
W
W/
°
C
W
Y
WW
G
= Year
= Work Week
= Pb−Free Package
D
C
Operating and Storage
T
e
mperature Range
T , T
−
5
5 to
150
°
C
J
stg
ORDERING INFORMATION
Single Pulse Drain−to−Source Avalanche
E
300
mJ
AS
†
Device
Package
DPAK
Shipping
Energy − Starting T
= 25
°
C
J
(V =
25 Vdc, V
= 5.0 Vdc,
DD
GS
MTD20P06HDL
75 Units/Rail
I =
15 Apk, L = 2.7 mH, R
= 25
W
)
L
G
MTD20P06HDLT4
MTD20P06HDLT4G
DPAK
2500
T
a
pe & Reel
2500
T
a
pe & Reel
Thermal Resistance
− Junction−to−Case
°
C/W
°
C
R
R
R
1.73
100
71.4
q
JC
JA
JA
DPAK
(Pb−Free)
q
q
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specification
Brochure, BRD8011/D.
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8
″
from case for 10 seconds
T
260
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When
surface mounted to an FR4 board using the minimum recommended
pad size.
Preferred
devices are recommended choices for future use
and best overall value.
2. When
surface mounted to an FR4 board using 0.5 sq. inch pad size.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MTD20P06HDL/D
MTD20P06HDL
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain−Source Breakdown Voltage
V
Vdc
mV/
°
C
m
Adc
(BR)DSS
(V =
0 Vdc, I
= 250
m
Adc)
60
−
−
81.3
−
−
GS
D
T
e
mperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
I
DSS
(V =
60 Vdc, V
= 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V =
60 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V
= 0)
−
−
100
nAdc
GS
DS
GSS
Gate Threshold Voltage
V
Vdc
mV/
°
C
m
W
GS(th)
(V =
V ,
I =
250
m
Adc)
1.0
−
1.7
3.9
2.0
−
DS
GS
D
T
e
mperature Coefficient (Negative)
Static Drain−Source On−Resistance
R
V
−
143
175
DS(on)
(V =
5.0 Vdc,
I =
7.5 Adc)
GS
D
Drain−Source On−Voltage (V
= 5.0 Vdc)
Vdc
GS
DS(on)
(I =
15 Adc)
(I =
7.5 Adc, T
= 125
°
C)
D
−
−
2.3
1.6
3.0
2.0
D
J
Forward Transconductance (V
= 10
Vdc, I
= 7.5 Adc)
g
FS
9.0
11
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
−
−
−
850
210
66
1190
290
130
Output Capacitance
C
oss
(V =
25 Vdc, V
= 0 Vdc, f = 1.0 MHz)
DS
GS
Reverse Transfer Capacitance
C
rss
Turn−On Delay Time
Rise Time
t
−
−
−
−
−
−
−
−
19
175
41
38
350
82
136
29
−
ns
d(on)
t
r
(V =
30 Vdc, I
= 15 Adc,
DS
GS
D
V
= 5.0 Vdc,R
= 9.1
W
)
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
68
f
Gate Charge
Q
T
Q
1
Q
2
Q
3
20.6
3.7
7.6
8.4
nC
(V =
48 Vdc, I
= 15
Adc,
DS
D
V
= 5.0 Vdc)
GS
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I =
15 Adc, V
= 0 Vdc)
S
GS
−
−
2.5
1.9
3.0
−
(I =
15 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
64
50
−
−
−
−
rr
t
a
(I =
15 Adc, V
= 0 Vdc,
S
GS
dI /dt
= 100 A/
m
s)
S
t
14
b
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
Q
0.177
m
C
RR
L
−
−
4.5
7.5
−
−
nH
nH
D
(Measured from the drain lead 0.25
″
from package to center of die)
Internal Source Inductance
L
S
(Measured from the source lead 0.25
″
from package to source bond pad)
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperature.
2
MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
30
25
30
V
= 10 V
T =
25
°
C
J
V
≥
5 V
DS
9 V
GS
8 V
7 V
6 V
25
20
15
10
5
25
°
C
T =
−ꢀ55
°
C
J
20
15
10
5
100
°
C
5 V
4 V
0
0
0
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.40
0.32
0.24
0.16
0.08
0
0.275
0.250
V
= 5 V
T =
25
°
C
GS
J
0.225
0.200
0.175
0.150
T =
100
°
C
J
25
°
C
V
= 5 V
GS
−ꢀ55
°
C
10 V
15
0.125
0.100
0
5
10
15
20
25
30
0
5
10
20
25
30
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100
10
1
1.8
1.6
1.4
1.2
1
V
= 0 V
V
= 5 V
I =
7.5 A
GS
GS
D
T =
125
°
C
J
100
°
C
0.8
0.6
0.4
0.2
0
−ꢀ50
−ꢀ25
0
25
50
75
100
125
150
0
10
V
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
3
MTD20P06HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
2500
V
= 0 V
T =
25
°
C
J
V
= 0 V
DS
GS
C
iss
2000
1500
1000
500
0
C
rss
C
iss
C
oss
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
4
MTD20P06HDL
6
5
4
3
2
1
0
1000
50
45
V
I =
15 A
= 30 V
QT
DD
D
V
= 5.0 V
GS
40
35
30
25
20
15
10
5
t
r
T =
25
°
C
J
100
t
f
V
V
DS
GS
t
d(off)
Q1
Q2
t
d(on)
I =
15 A
D
10
1
T =
25
°
C
J
Q3
4
0
24
0
8
12
16
20
1
10
R ,
GATE RESISTANCE (Ohms)
100
Q ,
TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
15
V
= 0 V
GS
T =
25
°
C
J
12
9
6
3
0
0.5
0.75
V
1
1.25
1.5
1.75
2
2.25
2.5
, SOURCE−TO−DRAIN VOLTAGE (Volts)
SD
Figure 10. Diode Forward Voltage versus Current
5
MTD20P06HDL
di/dt = 300 A/
m
s
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded, and that the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t , t ) does not exceed 10
m
s. In addition the
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
r
f
total power averaged over a complete switching cycle must
not exceed (T
− T
)/(R ).
energy at currents below rated continuous I
can safely be
D
J(MAX)
C
q
JC
assumed to equal the values indicated.
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
100
300
V
= 20 V
SINGLE PULSE
GS
I =
15 A
D
T =
25
°
C
C
240
180
120
60
100
m
s
10
1 ms
10 ms
dc
1.0
0.1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0
0.1
1.0
10
100
25
50
75
100
125
150
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6
MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
0.05
0.02
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
0.01
t
2
T
− T
= P
C
R
(t)
q
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
SINGLE PULSE
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
1.0E+01
t, TIME (s)
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 15. Diode Reverse Recovery Waveform
7
MTD20P06HDL
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
NOTES:
SE
A
T
ING
PLANE
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
B
R
INCHES
DIM MIN
MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D
2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
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to any products herein.
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
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ll Free USA/Canada
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: 303−675−2176 or 800−344−3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MTD20P06HDL/D
