onsemi-MTP1306
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MTP1306
Preferred Device
Power MOSFET
75 Amps, 30 Volts
N−Channel TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating area are critical and offer additional safety margin
against unexpected voltage transients.
75 AMPERES
30 VOLTS
R
DS(on)
= 6.5 m
Ω
•
Avalanche Energy Specified
N−Channel
•
Source−to−Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
D
•
Diode is Characterized for Use in Bridge Circuits
•
I
and V
Specified at Elevated Temperature
DSS
DS(on)
G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
S
Rating
Symbol
Value
30
Unit
Vdc
Vdc
Drain−to−Source Voltage
V
V
DSS
Drain−to−Gate Voltage (R
= 1.0 M
Ω
)
30
MARKING DIAGRAM
GS
DGR
& PIN ASSIGNMENT
Gate−to−Source Voltage
− Continuous
4
V
V
GSM
±
20
±
20
Vdc
Vpk
GS
4
Drain
− Non−Repetitive (t
≤
10 ms)
p
Drain Current
− Continuous
− Continuous @ 100
°
C
− Single Pulse (t
≤
10
µ
s)
I
I
75
59
225
Adc
Apk
D
D
TO−220AB
CASE 221A
STYLE 5
I
DM
p
MTP1306
LLYWW
T
o
tal Power Dissipation
Derate above 25
°
C
P
150
1.2
Watts
W/
°
C
D
1
Gate
3
1
Operating and Storage
T
e
mperature
Range
T , T
−
5
5 to
150
°
C
2
J
stg
Source
3
2
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Drain
Energy − Starting T
= 25
°
C
280
J
(V =
25 Vdc, V
= 10 Vdc, Peak
DD
GS
MTP1306
LL
Y
WW
= Device Code
= Location Code
=
Y
e
ar
I =
75 Apk, L = 0.1 mH, R
= 25
Ω
)
L
G
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
°
C/W
°
C
R
R
0.8
62.5
θ
JC
JA
= Work Week
θ
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8
″
from Case for 5.0
seconds
T
260
ORDERING INFORMATION
L
Device
MTP1306
Package
Shipping
50 Units/Rail
TO−220AB
Preferred
devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
September, 2004 − Rev. XXX
MTP1306/D
MTP1306
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
Vdc
(BR)DSS
(V =
0 Vdc, I
= 0.25 mAdc)
30
−
−
GS
D
Zero Gate Voltage Drain Current
(V =
30 Vdc, V
= 0 Vdc)
I
µ
Adc
DSS
−
−
−
−
10
100
DS
GS
(V =
30 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
±
20 Vdc, V
= 0 Vdc)
I
−
−
100
nAdc
GS
DS
GSS
Gate Threshold Voltage
(V =
V ,
I =
250
µ
Adc)
V
GS(th)
Vdc
1.0
1.5
2.0
DS
GS
D
Static Drain−to−Source On−Resistance
(V =
10 Vdc, I
= 38 Adc)
R
m
W
DS(on)
−
−
5.8
7.4
6.5
8.5
GS
D
(V =
5.0 Vdc, I
= 38 Adc)
GS
D
Drain−to−Source On−Voltage
(V =
10 Vdc, I
= 75 Adc)
V
DS(on)
Vdc
−
−
0.44
−
0.5
0.38
GS
D
(V =
10 Vdc, I
= 38 Adc, T
= 150
°
C)
GS
D
J
Forward Transconductance (V
= 3.0 Vdc, I
= 20 Adc)
g
FS
15
55
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
C
−
−
−
2560
1305
386
3584
1827
772
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
C
rss
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
17
170
68
35
340
136
290
70
−
ns
d(on)
(V =
15 Vdc, I
= 75 Adc,
DD
D
Rise Time
t
r
V
GS
= 5.0 Vdc,
Turn−Off Delay Time
Fall Time
t
d(off)
R
= 4.7
Ω
)
G
t
f
145
50
Gate Charge
Q
T
Q
1
Q
2
Q
3
nC
8.3
(V =
24 Vdc, I
= 75 Adc,
DS
D
V
GS
= 5.0 Vdc)
25.3
17.2
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I =
20 Adc, V
= 0 Vdc)
−
−
0.75
0.64
1.1
−
S
GS
(I =
20 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
84
35
−
−
−
−
rr
t
a
(I =
20 Adc, V
= 0 Vdc,
S
GS
t
53
b
dI /dt
= 100 A/
µ
s)
S
Reverse Recovery Stored
Charge
Q
0.13
µ
C
RR
1. Pulse
T
e
st: Pulse Width
≤
300
µ
s, Duty Cycle
≤
2%.
2. Switching
characteristics are independent of operating junction temperature.
2
MTP1306
TYPICAL ELECTRICAL CHARACTERISTICS
150
125
100
75
180
V
GS
= 10 V
5.0 V
V
DS
≥
10 V
160
140
120
100
80
4.0 V
T = 25
°
C
J
50
60
25
°
C
40
25
0
125
°
C
20
0
T = −55
°
C
J
0
0.25
0.5
0.75
1.0
1.25
1.5
1.75
2.0
2.0
2.5
3.0
3.5
4.0
4.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.009
0.008
0.007
0.006
V
GS
≥
10 V
T = 25
°
C
J
T = 100
°
C
J
V
GS
= 5.0 V
25
°
C
−55
°
C
10 V
0.005
0.004
0.001
0
20
40
60
80
100
120
140
20 30
40 50 60 70 80 90
100 110 120 130 140 150
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10,000
1000
2.0
1.5
1.0
V
= 10 V
GS
= 38 A
I
D
T = 125
°
C
J
100
10
100
°
C
0.5
0
−50
−25
0
25
50
75
100
125
150
5.0
10
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
V
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
3
MTP1306
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
∆
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
9000
V
DS
= 0 V
V
GS
= 0 V
8000
7000
6000
5000
4000
3000
2000
1000
0
C
iss
C
rss
C
iss
C
C
oss
rss
−10
−5.0
0
5.0
10
15
20
25
V
GS
V
DS
V
GS
OR V
, GATE−TO−SOURCE OR DRAIN−TO−SOURCE
DS
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
MTP1306
10
7.5
5.0
18
15
12
9.0
6.0
10,000
V
= 15 V
DD
= 75 A
I
D
V
GS
= 5.0 V
T =
25
°
C
J
1000
QT
V
GS
t
t
r
Q1
Q2
f
100
10
t
d(off)
2.5
0
T =
25
°
C
3.0
0
J
Q3
I
= 75 A
t
D
d(on)
V
DS
1.0
10
R ,
GATE RESISTANCE (OHMS)
100
0
10
20
30
40
50
60
Q ,
TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
20
V
= 0 V
GS
18
16
T =
25
°
C
J
14
12
10
8.0
6.0
4.0
2.0
0
0.45
0.50
0.55
0.60
0.65
0.70
0.75
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
5
MTP1306
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10
µ
s. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T
)/(R ).
energy at currents below rated continuous I
can safely be
J(MAX)
C
θ
JC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
assumed to equal the values indicated.
280
1000
V
= 10 V
SINGLE PULSE
GS
I
D
= 75 A
240
200
160
120
80
T
= 25
°
C
C
100
10
1.0 ms
10 ms
dc
1.0
0.1
R
LIMIT
DS(on)
40
0
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
6
MTP1306
1.0
D = 0.5
0.2
0.1
P
0.1
(pk)
0.05
0.02
R
(t) = r(t) R
θ
JC
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
0.01
SINGLE PULSE
1.0E−05 1.0E−04
t
2
T
− T
= P
C
R (t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−03
1.0E−02
1.0E−01
1.0E+00
1.0E+01
t, TIME (s)
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 15. Diode Reverse Recovery Waveform
7
MTP1306
PACKAGE DIMENSIONS
TO−220 THREE−LEAD
TO−220AB
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING
DIMENSION: INCH.
3. DIMENSION
Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
1
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor
and
are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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without further notice to any products herein.
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including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time.
All operating parameters, including “Typicals” must be
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.
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MTP1306/D
