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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP4N40E/D
Designer’s Data
Sheet
TMOS E−FE
T
.
MTP4N40E
Motorola Preferred Device
Power Field Effect Transistor
N−Channel Enhancement−Mode Silicon Gate
TMOS POWER FET
4.0 AMPERES
400 VOLTS
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage−blocking capability without
degrading performance over time. In addition, this advanced TMOS
E−FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
R
DS(on)
= 1.8 OHM
D
•
•
•
Robust High Voltage
T
e
rmination
Avalanche Energy Specified
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
G
•
•
Diode is Characterized for Use in Bridge Circuits
S
I
DSS
and V
DS(on)
Specified at Elevated
T
e
mperature
CASE 221A−06, Style 5
TO−220AB
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
Rating
Symbol
Value
400
Unit
Vdc
Vdc
Drain−to−Source Voltage
V
DSS
DGR
Drain−to−Gate Voltage (R
= 1.0 M
Ω
)
V
V
400
GS
Gate−to−Source Voltage
— Continuous
V
GS
±
20
±
40
Vdc
Vpk
— Non−Repetitive (t
≤
10 ms)
p
GSM
Drain Current
— Continuous
— Continuous @ 100
°
C
— Single Pulse (t
≤
10
µ
s)
I
I
4.0
3.0
14
Adc
Apk
D
D
I
p
DM
T
o
tal Power Dissipation
P
D
74
Watts
Derate above 25
°
C
0.59
W/
°
C
Operating and Storage
T
e
mperature Range
T , T
−
5
5 to 150
°
C
J
stg
Single Pulse Drain−to−Source Avalanche Energy — Starting T
= 25
°
C
E
AS
mJ
J
(V =
25 Vdc, V
= 10 Vdc, Peak I
= 4.0 Apk, L = 25 mH, R
= 25
Ω
)
200
DD
GS
L
G
Thermal Resistance — Junction to Case
— Junction to Ambient
R
R
1.7
62.5
°
C/W
°
C
θ
JC
JA
θ
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8
″
from case for 10 seconds
T
260
L
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola, Inc. 1996
MTP4N40E
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
(BR)DSS
(V =
0 Vdc, I
= 0.25 mAdc)
T
e
mperature Coefficient (Positive)
400
—
—
420
—
—
Vdc
mV/
°
C
GS
D
Zero Gate Voltage Drain Current
I
µ
Adc
DSS
(V =
400 Vdc, V
= 0 Vdc)
—
—
—
—
10
100
DS
GS
(V =
400 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
±
20 Vdc, V
= 0 Vdc)
I
—
—
100
nAdc
GS
DS
GSS
(1)
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
(V =
V ,
I =
250
µ
Adc)
Threshold
T
e
mperature Coefficient (Negative)
2.0
—
3.0
6.0
4.0
—
Vdc
mV/
°
C
DS
GS
D
Static Drain−to−Source On−Resistance (V
= 10 Vdc, I
= 2.0 Adc)
R
V
—
1.3
1.8
Ohms
Vdc
GS
D
DS(on)
Drain−to−Source On−Voltage
(V =
10 Vdc, I
= 4.0 Adc)
DS(on)
—
—
—
—
8.6
4.3
GS
D
(V =
10 Vdc, I
= 2.0 Adc, T
= 125
°
C)
GS
D
J
Forward Transconductance (V
= 15 Vdc, I
= 2.0 Adc)
g
FS
1.8
2.5
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
440
72
616
100
19.6
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
14
rss
(2)
SWITCHING CHARACTERISTICS
Turn−On Delay Time
t
—
—
—
—
—
—
—
—
9.0
11
20
30
30
30
21
—
—
—
ns
d(on)
(V =
200 Vdc, I
= 4.0 Adc,
DD
D
Rise Time
t
r
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
18
d(off)
R
= 9.1
Ω
)
G
t
f
14
Gate Charge
Q
T
Q
1
Q
2
Q
3
13
nC
2.5
6.0
7.0
(V =
320 Vdc, I
= 4.0 Adc,
DS
D
V
GS
= 10 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I =
4.0 Adc, V
= 0 Vdc)
S
GS
—
—
0.9
0.78
1.6
—
(I =
4.0 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
t
—
—
—
—
200
99
—
—
—
—
rr
t
a
(I =
4.0 Adc, V
= 0 Vdc,
S
GS
dI /dt
= 100 A/
µ
s)
S
t
101
1.03
b
Reverse Recovery Stored Charge
Q
µ
C
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
L
D
nH
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25
″
from package to center of die)
—
—
3.5
4.5
—
—
Internal Source Inductance
L
S
nH
(Measured from the source lead 0.25
″
from package to source bond pad)
—
7.5
—
(1) Pulse
T
e
st: Pulse Width
≤
300
µ
s, Duty Cycle
≤
2%.
(2) Switching
characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N40E
TYPICAL ELECTRICAL CHARACTERISTICS
8
7
6
5
4
3
2
8
V
GS
= 10 V
T = 25
°
C
J
V
DS
≥
10 V
9 V
8 V
7
6
5
4
3
2
1
0
7 V
6 V
5 V
100
°
C
1
0
25
°
C
T = −55
°
C
J
0
2
4
6
8
10
12
14
16
18
20
2
2.5
3
3.5
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
4
3.5
3
2.25
2
V
GS
= 10 V
T = 25
°
C
J
T = 100
°
C
J
1.75
1.5
1.25
1
V
GS
= 10 V
2.5
2
15 V
25
°
C
1.5
1
−
5
5
°
C
0.75
0.5
0.5
0
0
1
2
3
4
5
6
7
8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.5
2.25
2.0
1000
100
10
V
= 10 V
V
GS
= 0 V
GS
I
D
= 2 A
T = 125
°
C
J
1.75
100
°
C
1.5
1.25
1.0
0.75
0.5
0.25
0
−50
1
−25
0
25
50
75
100
125
150
0
50
V
100
150
200
250
300
350
400
T , JUNCTION TEMPERATURE (
°
C)
J
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTP4N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
∆
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when cal-
culating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFE
T
s
h
ave finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure
9) shows how typical switching performance is
affected by the parasitic circuit elements.
If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed.
The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components.
Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load.
Power MOSFE
T
s
m
ay be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain−gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In
most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V
GS
remains virtually constant at a level known as
the plateau voltage, V
SG
P
. Therefore,
rise and fall times may
be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
t
f
= Q
2
x R
G
/V
GSP
where
)
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant.
The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
800
700
600
V
DS
= 0 V
V
GS
= 0 V
T = 25
°
C
J
C
iss
500
400
300
200
C
rss
C
iss
C
oss
100
0
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N40E
12
100
10
1
600
550
500
450
400
350
300
250
200
QT
V
DD
= 200 V
11
10
9
I
D
= 4 A
V
= 10 V
GS
T =
25
°
C
J
8
Q1
Q2
t
d(off)
V
7
GS
t
f
t
r
6
t
d(on)
5
4
T =
25
°
C 150
3
J
I
= 4 A
D
100
2
Q3
50
0
1
0
V
DS
1
10
R ,
GATE RESISTANCE (OHMS)
100
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Q ,
TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
4
V
= 0 V
GS
T =
25
°
C
3.6
3.2
2.8
2.4
J
2
1.6
1.2
0.8
0.4
0
0.5
0.55
V
0.6
0.65
0.7
0.75
0.8
0.85
0.9
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (T
C
) of 25
°
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non−linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E−FE
T
s
c
an withstand the stress of drain−
to−source avalanche at currents up to rated pulsed current
(I
DM
), the energy rating is specified at rated continuous cur-
rent (I
D
), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous I
D
can safely be assumed to
equal the values indicated.
Switching between the off−state and the on−state may tra-
verse any load line provided neither rated peak current (I
DM
)
nor rated voltage (V
DSS
) is exceeded and the transition time
(t
r
,t
f
) do not exceed 10
µ
s. In addition the total power aver-
aged over a complete switching cycle must not exceed
(T
J(MAX)
− T
C
)/(R
θ
JC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
5
MTP4N40E
SAFE OPERATING AREA
200
180
160
100
V
= 20 V
I =
4 A
D
GS
SINGLE PULSE
T
= 25
°
C
C
10
10ꢀ
µ
s
140
120
100
80
60
40
20
0
100ꢀ
µ
s
1.0
0.1
1ꢀms
10ꢀms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
10
100
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.05
0.1
R
θ
(t) = r(t) R
θ
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
0.01
t
1
READ TIME AT t
1
t
2
T
− T
= P
C
R (t)
θ
JC
J(pk)
(pk)
SINGLE PULSE
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP4N40E
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING
DIMENSION: INCH.
3. DIMENSION
Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
−−−
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
STYLE 5:
1
2
3
U
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
0.080
2.04
CASE 221A−06
(TO−220AB)
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
7
MTP4N40E
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages.
“Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
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Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MTP4N40E/D
◊
*MTP4N40E/D*
