onsemi-MTSF3N02HDR2
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MTSF3N02HD
Preferred Device
Power MOSFET
3 Amps, 20 Volts
N
−
Channel Micro8
t
These Power MOSFET devices are capable of withstanding high
energy in the avalanche and commutation modes and the drain
−
to
−
source
diode has a very low reverse recovery time. Micro8 devices are designed
for use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc
−
dc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
3 AMPERES
20 VOLTS
R
DS(on)
= 40 m
W
N
−
Channel
D
•
Miniature Micro8 Surface Mount Package
−
Saves Board Space
•
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
G
•
Ultra Low R
Provides Higher Efficiency and Extends Battery
DS(on)
Life
S
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
MARKING
DIAGRAM
•
I
Specified at Elevated Temperature
DSS
•
Avalanche Energy Specified
•
Mounting Information for Micro8 Package Provided
Micro8
CASE 846A
STYLE 1
8
WW
AC
1
WW
= Date Code
PIN ASSIGNMENT
Source
1
8
7
6
5
Drain
Drain
Drain
Drain
2
3
4
Source
Source
Gate
T
o
p View
ORDERING INFORMATION
Device
Package
Shipping
4000
T
a
pe & Reel
MTSF3N02HDR2
Micro8
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
August, 2006
−
Rev. 6
MTSF3N02HD/D
MTSF3N02HD
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol
Max
20
Unit
V
Drain
−
to
−
Source Voltage
V
DSS
DGR
Drain
−
to
−
Gate Voltage (R
= 1.0 M
Ω
)
V
20
V
GS
Gate
−
to
−
Source Voltage
−
Continuous
V
GS
±
8.0
V
1
″
SQ.
FR
−
4 or G
−
10 PCB
Figure 1 below
Thermal Resistance
−
Junction to Ambient
R
70
1.79
14.29
6.1
°
C/W
Watts
mW/
°
C
A
THJA
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
A
Linear Derating Factor
I
D
Drain Current
−
Continuous @ T
= 25
°
C
A
I
D
4.9
A
Continuous @ T
= 70
°
C
A
I
49
A
Steady State
DM
Minimum
FR
−
4 or G
−
10 PCB
Figure 2 below
Thermal Resistance
−
Junction to Ambient
R
160
0.78
6.25
4.0
°
C/W
Watts
mW/
°
C
A
THJA
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
A
Linear Derating Factor
I
D
Drain Current
−
Continuous @ T
= 25
°
C
A
I
D
3.2
A
Continuous @ T
= 70
°
C
A
I
32
A
Steady State
DM
Operating and Storage
T
e
mperature Range
T , T
−
55 to 150
°
C
J
stg
1. Repetitive
rating; pulse width limited by maximum junction temperature.
Figure 1. 1
,
Square FR
−
4 or G
−
10 PCB
Figure 2. Minimum FR
−
4 or G
−
10 PCB
2
MTSF3N02HD
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
(V =
0 Vdc, I
= 250
μ
Adc)
T
e
mperature Coefficient (Positive)
(Cpk
≥
2.0)
V
Vdc
(BR)DSS
20
−
−
16
−
−
GS
D
mV/
°
C
μ
Adc
Zero Gate Voltage Drain Current
I
DSS
(V =
16 Vdc, V
= 0 Vdc)
−
−
−
−
1.0
25
DS
GS
(V =
16 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate
−
Body Leakage Current (V
=
±
8.0 Vdc, V
= 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
GSS
Gate Threshold Voltage
(V =
V ,
I =
250
μ
Adc)
(Cpk
≥
2.0)
V
GS(th)
0.7
−
0.98
2.65
1.1
−
DS
GS
D
Threshold
T
e
mperature Coefficient (Negative)
mV/
°
C
m
Ω
Static Drain
−
to
−
Source On
−
Resistance (Cpk
≥
2.0)
R
DS(on)
(V =
4.5 Vdc, I
= 3.8 Adc)
−
−
30
40
40
50
GS
D
(V =
2.7 Vdc, I
= 1.9 Adc)
GS
D
Forward Transconductance (V
= 10 Vdc, I
= 1.9 Adc)
g
FS
4.0
7.5
−
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
C
−
−
−
475
255
110
−
−
−
iss
(V =
15 Vdc, V
= 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
C
rss
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
−
−
−
−
−
9.5
45
−
−
ns
ns
d(on)
Rise Time
t
r
(V =
10 Vdc, I
= 3.8 Adc,
DS
D
V
GS
G
Turn
−
Off Delay Time
Fall Time
t
t
t
50
−
d(off)
t
f
62
−
Turn
−
On Delay Time
Rise Time
19
−
d(on)
t
r
130
38
−
(V =
10 Vdc, I
= 1.9 Adc,
DD
D
V
GS
G
Turn
−
Off Delay Time
Fall Time
−
d(off)
t
f
47
−
Gate Charge
Q
T
Q
1
Q
2
Q
3
12
17
−
nC
1.0
5.0
3.5
(V =
16 Vdc, I
= 3.8 Adc,
DS
D
V
GS
= 4.5 Vdc)
−
−
SOURCE
−
DRAIN DIODE CHARACTERISTICS
Forward On
−
Voltage
V
SD
Vdc
ns
S
GS
(I =
3.8 Adc, V
= 0 Vdc,
−
−
0.83
0.68
1.0
−
S
GS
T =
125
°
C)
J
Reverse Recovery Time
t
rr
−
−
−
−
46
23
−
−
−
−
(I =
3.8 Adc, V
= 0 Vdc,
S
GS
t
a
S
t
b
23
Reverse Recovery Storage Charge
Q
0.05
μ
C
RR
2. Pulse
T
e
st: Pulse Width
≤
300
μ
s, Duty Cycle
≤
2%.
3. Switching
characteristics are independent of operating junction temperature.
4. Reflects
typical values.
Max limit
−
Typ
C
=
pk
3 x SIGMA
3
MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
8
7
6
5
4
3
2
1
0
8
T = 25
°
C
V
= 10 V
J
GS
V
DS
≥
10 V
7
6
5
4
3
2
1
0
4.5 V
2.9 V
2.5 V
1.9 V
2.3 V
2.1 V
1.7 V
1.5 V
T =
−55
°
C
J
25
°
C
100
°
C
0
0.4
0.8
1.2
1.6
2
1
1.2
1.4
1.6
1.8
2
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 3. On
−
Region Characteristics
Figure 4. Transfer Characteristics
0.06
0.05
0.04
0.03
0.02
0.01
0.06
0.05
0.04
0.03
0.02
0.01
T = 25
°
C
V
= 3.8 V
J
GS
T =
25
°
C
J
V
GS
= 2.7 V
4.5 V
0
2
4
6
8
0
1
2
5
6
7
8
3
4
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I ,
DRAIN CURRENT (AMPS)
D
Figure 5. On
−
Resistance versus
Gate
−
to
−
Source Voltage
Figure 6. On
−
Resistance versus Drain Current
and Gate Voltage
2.0
1000
100
V
GS
I =
1.9 A
= 4.5 V
V
GS
= 0 V
T =
125
°
C
J
D
1.5
1.0
0.5
0
100
°
C
10
1
25
°
C
0.1
0
4
8
12
16
20
−ꢀ50
−ꢀ25
0
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 7. On
−
Resistance Variation
Figure 8. Drain
−
to
−
Source Leakage Current
with Temperature
versus Voltage
4
MTSF3N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
Δ
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off
−
state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on
−
state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
11) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
−
V )
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn
−
on and turn
−
off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
−
V )]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
2500
2000
T = 25
°
C
J
C
C
iss
V
GS
= 0 V
rss
1500
1000
C
iss
500
0
C
oss
C
rss
8
4
0
4
8
12
16
20
V
GS
V
DS
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 9. Capacitance Variation
5
MTSF3N02HD
6
5
4
3
2
18
15
1000
V
= 10 V
I =
3.8 A
DD
D
QT
V
GS
= 4.5 V
T =
25
°
C
J
V
V
100
12
9
GS
DS
t
r
t
f
t
t
d(off)
Q1
Q2
6
3
0
10
1
d(on)
1
0
I =
3.8 A
D
Q3
T =
25
°
C
J
0
3
6
9
12
15
1
10
R ,
GATE RESISTANCE (OHMS)
100
Q ,
TOTAL GATE CHARGE (nC)
g
G
Figure 10. Gate
−
To
−
Source and
Drain
−
T
o
−
Source Voltage versus Total Charge
Figure 11. Resistive Switching Time
Variation versus Gate Resistance
DRAIN
−
TO
−
SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
4
V
GS
= 0 V
T =
25
°
C
J
3
2
1
0
0.4
0.5
0.6
0.7
0.8
0.9
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 12. Diode Forward Voltage versus Current
6
MTSF3N02HD
di/dt = 300 A/
μ
s
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 13. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
Switching between the off
−
state and the on
−
state may
maximum simultaneous drain
−
to
−
source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
traverse any load line provided neither rated peak current
(I )
nor rated voltage (V
DM
) is exceeded, and that the
DSS
transition time (t , t ) does not exceed 10
μ
s. In addition
r
f
temperature and a case temperature (T ) of 25
°
C. Peak
the total power averaged ove
r
a
c
omplete switching cycle
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General
Data and Its Use.”
must not exceed (T
−
T )/(R
).
J(MAX) C
θ
JC
100
V
= 8 V
SINGLE PULSE
GS
T =
25
°
C
C
100
μ
s
10
1
1 ms
10 ms
dc
0.1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 14. Maximum Rated Forward Biased
Safe Operating Area
7
MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000
100
10
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
R
θ
(t) = r(t) R
θ
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
1.0
0.1
t
1
1
t
2
T
− T
= P
C
R (t)
θ
JC
J(pk)
(pk)
SINGLE PULSE
1.0E−04
DUTY CYCLE, D = t
/t
1
2
1.0E−05
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
1.0E+03
Figure 15. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 16. Diode Reverse Recovery Waveform
8
MTSF3N02HD
INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self
−
align when
subjected to a solder reflow
process.
0.041
1.04
0.208
5.28
0.126
3.20
0.015
0.38
0.0256
0.65
inches
mm
Micro8 POWER DISSIPATION
The power dissipation of the Micro8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
into the equation for an ambient temperature T
of 25
°
C,
one can calculate the power dissipation of the device which
in this case is 0.78 Watts.
A
150
°
C
−
25
°
C
= 0.78
Watts
P
D
=
determined by T
, the maximum rated junction
J(max)
160
°
C/W
temperature of the die, R
, the thermal resistance from
θ
JA
The 160
°
C/W for the Micro8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 0.78 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Clad
t
. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
the device junction to ambient; and the operating
temperature, T . Using the values provided on the data
A
sheet for the Micro8 package, P
can be calculated as
D
follows:
T
J(max)
−
T
A
P
D
=
R
θ
JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•
Always preheat the device.
•
The delta temperature between the preheat and
soldering should be 100
°
C or less.*
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10
°
C.
•
The soldering temperature and time shall not exceed
260
°
C for more than 10 seconds.
•
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
°
C or less.
•
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•
Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
9
MTSF3N02HD
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 17
7
−
189
°
C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 14 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES
2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
205
°
TO 219
°
C
PEAK AT
SOLDER
JOINT
170
°
C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
200
°
C
150
°
C
100
°
C
5
°
C
160
°
C
150
°
C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100
°
C
140
°
C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 17. Typical Solder Heating Profile
10
MTSF3N02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)
2.05 (.080)
1.95 (.077)
0.35 (.013)
0.25 (.010)
1.85 (.072)
1.65 (.065)
4.10 (.161)
3.90 (.154)
PIN
B
B
A
NUMBER 1
5.55 (.218)
5.45 (.215)
12.30
11.70
(.484)
(.461)
3.50 (.137)
3.30 (.130)
1.60 (.063)
1.50 (.059)
TY
P
.
1.50 (.059)
1.30 (.052)
A
FEED DIRECTION
8.10 (.318)
7.90 (.312)
SECTION A
−
A
5.40 (.212)
5.20 (.205)
SECTION B
−
B
NOTES:
1. CONFORMS
TO EIA
−
481
−
1.
2. CONTROLLING
DIMENSION: MILLIMETER.
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.
50.0
(1.97)
MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
1. CONFORMS
TO EIA
−
481
−
1.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. INCLUDES
FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION
MEASURED AT INNER HUB.
11
MTSF3N02HD
PACKAGE DIMENSIONS
Micro8
CASE 846A
−
02
ISSUE E
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
−
A
−
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION
B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
−
B
−
K
MILLIMETERS
INCHES
PIN 1 ID
G
DIM MIN
MAX
3.10
3.10
1.10
MIN
MAX
0.122
0.122
0.043
0.016
D
8 PL
A
B
C
D
G
H
J
2.90
2.90
−−−
0.114
0.114
−−−
M
S
S
0.08 (0.003)
T B
A
0.25
0.40 0.010
0.65 BSC
0.026 BSC
0.05
0.13
4.75
0.40
0.15 0.002
0.23 0.005
5.05 0.187
0.70 0.016
0.006
0.009
0.199
0.028
SEATING
PLANE
−
T
−
K
L
C
0.038 (0.0015)
STYLE 1:
PIN 1.
SOURCE
L
J
H
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
Micro8 is a trademark of International Rectifier. Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTSF3N02HD/D
