onsemi-MTV16N50E
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MTV16N50E
Advance Information
TMOS E−FE
T
.
™
Power Field Effect
Transistor
D
3
PAK for Surface Mount
N
−
Channel Enhancement
−
Mode Silicon
Gate
TMOS POWER FET
16 AMPERES, 500 VOLTS
R
DS(on)
= 0.40
W
This high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage
−
blocking capability without degrading
performance over time. In addition, this advanced TMOS E
−
FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain
−
to
−
source
diode with a fast recovery time. Designed for high speed switching
applications in power supplies, converters, PWM motor controls,
these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
3
D PAK
Surface Mount
CASE 433
−
01
Style 2
D
N
−
Channel
•
Robust High
V
o
ltage Termination
•
Avalanche Energy Specified
•
Source
−
to
−
Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
G
®
•
Diode is Characterized for Use in Bridge Circuits
S
•
I
and V
Specified at Elevated Temperature
DSS
DS(on)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
Rating
Symbol
Value
500
Unit
Vdc
Vdc
Vdc
Adc
Drain
−
to
−
Source Voltage
V
DSS
DGR
Drain
−
to
−
Gate Voltage (R
= 1.0 M
Ω
)
V
500
GS
Gate
−
to
−
Source Voltage — Continuous
V
GS
±
20
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
I
I
16
9.0
60
D
D
Drain Current
— Single Pulse (t
≤
10
μ
s)
I
Apk
p
DM
T
o
tal Power Dissipation
Derate above 25
°
C
T
o
tal Power Dissipation @ T
= 25
°
C (1)
P
D
180
1.4
2.0
Watts
W/
°
C
Watts
A
Operating and Storage
T
e
mperature Range
T , T
−
55 to 150
°
C
J
stg
Single Pulse Drain
−
to
−
Source Avalanche Energy — Starting T
= 25
°
C
E
AS
mJ
J
(V =
50 Vdc, V
= 10 Vdc, Peak I
= 16 Apk, L = 6.7 mH, R
= 25
Ω
)
860
DD
GS
L
G
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
R
R
R
0.7
62.5
35
°
C/W
°
C
θ
JC
JA
JA
θ
θ
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8
″
from case for 10 seconds
T
260
L
(1) When
surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
August, 2006
−
Rev. 1
MTV16N50E/D
MTV16N50E
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
Vdc
(BR)DSS
(V =
0 Vdc, I
= 250
μ
Adc)
T
e
mperature Coefficient (Positive)
500
—
—
520
—
—
GS
D
mV/
°
C
μ
Adc
Zero Gate Voltage Drain Current
I
DSS
(V =
500 Vdc, V
= 0 Vdc)
—
—
—
—
250
1000
DS
GS
(V =
500 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate
−
Body Leakage Current (V
=
±
20 Vdc, V
= 0)
I
—
—
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V =
V ,
I =
250
μ
Adc)
Threshold
T
e
mperature Coefficient (Negative)
2.0
—
3.2
7.0
4.0
—
DS
GS
D
mV/
°
C
Ohm
Vdc
Static Drain
−
to
−
Source On
−
Resistance (V
= 10 Vdc, I
= 8.0 Adc)
R
V
—
0.32
0.40
GS
D
DS(on)
Drain
−
to
−
Source On
−
Voltage
(V =
10 Vdc, I
= 16 Adc)
DS(on)
—
—
—
—
6.7
5.6
GS
D
(V =
10 Vdc, I
= 8.0 Adc, T
= 125
°
C)
GS
D
J
Forward Transconductance (V
= 15 Vdc, I
= 8.0 Adc)
g
FS
5.0
—
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
C
—
—
—
3200
400
4480
560
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
C
320
448
rss
SWITCHING CHARACTERISTICS (2)
Turn
−
On Delay Time
t
—
—
—
—
—
—
—
—
28
80
80
60
65
17
47
34
60
160
160
120
—
ns
d(on)
(V =
250 Vdc, I
= 16 Adc,
DD
D
Rise Time
t
r
V
GS
= 10 Vdc,
Turn
−
Off Delay Time
Fall Time
t
d(off)
R
= 4.7
Ω
)
G
t
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
—
(V =
400 Vdc, I
= 16 Adc,
DS
D
V
GS
= 10 Vdc)
—
—
SOURCE
−
DRAIN DIODE CHARACTERISTICS
Forward On
−
Voltage
V
Vdc
ns
SD
(I =
16 Adc, V
= 0 Vdc)
S
GS
—
—
1.0
0.9
1.6
—
(I =
16 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
t
—
—
—
—
390
245
145
5.35
—
—
—
—
rr
t
a
(I =
16 Adc, V
= 0 Vdc,
S
GS
dI /dt
= 100 A/
μ
s)
S
t
b
Reverse Recovery Stored Charge
Q
μ
C
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″
from package to center of die)
L
nH
nH
D
—
—
5.0
13
—
—
Internal Source Inductance
(Measured from the source lead 0.25
″
from package to source bond pad)
L
S
(1) Pulse
T
e
st: Pulse Width
≤
300
μ
s, Duty Cycle
≤
2%.
(2) Switching
characteristics are independent of operating junction temperature.
2
MTV16N50E
TYPICAL ELECTRICAL CHARACTERISTICS
20
18
16
14
12
10
8
20
7 V
V
= 10 V
T = 25
°
C
J
V
DS
≥
10 V
GS
18
16
14
12
10
8
6 V
9 V
5 V
100
°
C
6
6
4
4
25
°
C
2
2
T = −55
°
C
4 V
9
J
0
0
0
1
2
3
4
5
6
7
8
10
0
1
2
3
4
5
6
7
8
9
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.4
0.35
0.3
V
GS
= 10 V
T = 25
°
C
J
T = 100
°
C
J
V
= 10 V
15 V
GS
25
°
C
0.25
0.2
−
5
5
°
C
0.15
25
30
0
5
10
15
20
25
30
35
0
5
10
15
20
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance versus Drain Current
Figure 4. On
−
Resistance versus Drain Current
and Temperature
and Gate Voltage
2.5
2.0
1.5
1.0
0.5
0
100000
10000
1000
100
V
GS
= 0 V
V
GS
I =
8 A
= 10 V
T = 125
°
C
J
D
100
°
C
25
°
C
10
−50
−25
0
25
50
75
100
125
150
0
100
200
300
400
5
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
To
−
Source Leakage
Temperature
Current versus Voltage
3
MTV16N50E
POWER MOSFET SWITCHING
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off
−
state condition when
calculating t
d(on)
and is read at a voltage corresponding to
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
Δ
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
the on
−
state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFE
T
s
h
ave
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The
circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components.
Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFE
T
s
m
ay be safely operated into an inductive
load; however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate
of average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SG
P
. Therefore,
rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
t
f
= Q
2
x R
G
/V
GSP
where
)
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn
−
on and turn
−
off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network.
The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
7000
10000
V
DS
= 0 V
V
GS
= 0 V
T = 25
°
C
J
V
GS
= 0
V
T = 25
°
C
J
C
iss
6000
5000
C
iss
1000
100
10
4000
3000
2000
1000
0
C
rss
C
iss
C
oss
C
rss
C
oss
C
rss
−10
−5
0
5
10
15
20
25
0
10
100
10
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 7a. Low Voltage Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
4
MTV16N50E
15
12
9
10000
500
400
300
200
T =
25
°
C
J
I =
16 A
t
d(off)
D
QT
V
DD
V
GS
= 250 V
= 10 V
V
GS
1000
t
d(on)
Q2
Q1
6
100
10
t
r
T =
25
°
C
J
I =
16 A
D
3
0
100
0
t
f
Q3
20
V
DS
0
10
30
40
50
60
70
80
90 100
1
10
100
10
Q ,
TOTAL GATE CHARGE (nC)
g
R ,
GATE RESISTANCE (OHMS)
G
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Voltage versus Total Charge
14
T =
25
°
C
J
V
GS
= 0 V
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non
−
linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E
−
FE
T
s
c
an withstand the stress of
drain
−
to
−
source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25
°
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance
−
General Data and Its Use.”
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
μ
s. In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
−
T
C
)/(R
θ
JC
).
A Power MOSFET designated E
−
FET can be safely used
in switching circuits with unclamped inductive loads. For
5
MTV16N50E
SAFE OPERATING AREA
900
800
700
600
500
400
300
200
100
10
V
= 20 V
SINGLE PULSE
GS
I =
16 A
D
T =
25
°
C
C
100
μ
s
1 ms
10 ms
dc
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
100
0
0.1
25
50
75
100
125
15
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
(pk)
R
θ
(t) = r(t) R
θ
JC
JC
0.01
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
− T
= P
C
R (t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t
/t
1 2
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
MTV16N50E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.165
4.191
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of R
θ
JA
versus drain pad area is shown in
Figure 15.
function of the drain pad size.
These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by T
J(max)
, the maximum rated
junction temperature of the die, R
θ
JA
, the thermal resistance
from the device junction to ambient, and the operating
temperature, T
A
. Using the values provided on the data
sheet, P
D
can be calculated as follows:
100
Board Material = 0.0625
″
G−10/FR−4, 2 oz Copper
1.75 Watts
80
T =
25
°
C
A
T
J(max)
−
T
A
P
D
=
R
θ
JA
60
3.0 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T
A
of 25
°
C, one can
calculate the power dissipation of the device. For a D
3
PAK
device, P
D
is calculated as follows.
40
5.0 Watts
20
0
2
4
6
8
10
150
°
C
−
25
°
C
A, AREA (SQUARE INCHES)
= 2.0
Watts
P
D
=
62.5
°
C/W
Figure 15. Thermal Resistance versus Drain Pad
Area for the D
3
PAK Package (Typical)
The 62.5
°
C/W for the D
3
PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
™
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
7
MTV16N50E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC
−
59, SC
−
70/SOT
−
323, SOD
−
123, SOT
−
23, SOT
−
143,
SOT
−
223, SO
−
8, SO
−
14, SO
−
16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D
2
PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D
2
PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D
2
PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•
Always preheat the device.
•
The delta temperature between the preheat and
soldering should be 100
°
C or less.*
•
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
°
C or less.
•
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•
Mechanical stress or shock should not be applied during
cooling.
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10
°
C.
•
The soldering temperature and time shall not exceed
260
°
C for more than 10 seconds.
* Soldering
a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due
to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D
2
PAK
is not recommended for wave soldering.
8
MTV16N50E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 17
7
−
189
°
C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed.
T
a
ken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 17 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
ꢀRAMP”
STEP 2
VENT
STEP 3
HEATING
STEP 4
HEATING
STEP 5
HEATING
STEP 6
VENT
STEP 7
COOLING
ꢀSOAK” ZONES
2 & 5
ꢀRAMP”
ZONES 3 & 6
ZONES 4 & 7
ꢀSOAK” ꢀSPIKE”
170
°
C
205
°
TO 219
°
C
PEAK AT
SOLDER JOINT
200
°
C
150
°
C
100
°
C
50
°
C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160
°
C
150
°
C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100
°
C
140
°
C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 17. Typical Solder Heating Profile
9
MTV16N50E
PACKAGE DIMENSIONS
CASE 433
−
01
ISSUE B
NOTES:
ꢁꢂ1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢁꢂ2. CONTROLLING
DIMENSION: INCH.
SEATING
−
T
−
PLANE
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
14.94
15.82
4.98
MAX
15.04
15.93
5.08
A
B
C
D
E
F
0.588
0.623
0.196
0.048
0.058
0.078
0.592
0.627
0.200
0.052
0.062
0.082
B
S
C
W
Y
R
E
Q
4
1.22
1.47
1.32
1.57
1.98
2.08
G
H
J
0.430 BSC
1.092 BSC
V
0.105
0.018
0.150
0.058
0.353
0.078
0.053
0.623
0.313
0.028
0.050
0.054
0.050
0.104
0.110
0.022
0.160
0.062
0.357
0.082
0.057
0.627
0.317
0.032
−−−
2.67
0.46
3.81
1.47
8.97
1.98
1.35
15.82
7.95
0.71
1.27
1.37
1.27
2.64
2.79
0.56
4.06
1.57
9.07
2.08
1.45
15.93
8.05
0.81
−−−
A
N
K
L
N
P
Q
R
S
U
V
W
X
Y
1
2
3
K
P
X
F
J
U
L
2 PL
H
D
2 PL
0.058
0.060
0.108
1.47
1.52
2.74
M
0.13 (0.005)
T
G
STYLE 2:
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
E
−
FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTV16N50E/D
