onsemi-MTW24N40E
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MTW24N40E
Preferred Device
Power MOSFET
24 Amps, 400 Volts
N−Channel TO−247
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced Power MOSFET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
24 AMPERES
400 VOLTS
DS(on)
= 160 m
Ω
R
N−Channel
D
•
Robust High
V
o
ltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
G
S
•
Diode is Characterized for Use in Bridge Circuits
•
I
and V
Specified at Elevated Temperature
4
DSS
DS(on)
•
Isolated Mounting Hole Reduces Mounting Hardware
TO−247AE
CASE 340K
Style 1
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
1
Rating
Drain−Source Voltage
Symbol
Value
400
Unit
Vdc
Vdc
2
3
MARKING DIAGRAM
& PIN ASSIGNMENT
V
DSS
DGR
Drain−Gate Voltage (R
= 1.0 M
Ω
)
V
400
GS
4
Drain
Gate−Source Voltage
− Continuous
V
±
20
±
40
Vdc
Vpk
GS
− Non−Repetitive (t
≤
10 ms)
V
GSM
p
Drain Current − Continuous
Drain Current
− Continuous @ 100
°
C
Drain Current
− Single Pulse (t
≤
10
µ
s)
I
I
24
17.7
72
Adc
Apk
D
MTW24N40E
LLYWW
D
I
DM
p
T
o
tal Power Dissipation
Derate above 25
°
C
P
D
250
2.0
Watts
W/
°
C
1
Gate
3
Operating and Storage
T
e
mperature Range
Single Pulse Drain−to−Source Avalanche
T , T
−
5
5 to
150
°
C
J
stg
Source
E
AS
600
mJ
2
Energy − Starting T
= 25
°
C
J
Drain
(V =
100 Vdc, V
= 10 Vdc,
DD
GS
LL
Y
= Location Code
=
Y
e
ar
I =
20 Apk, L = 3.0 mH, R
= 25
Ω
)
L
G
WW
= Work Week
Thermal Resistance − Junction to Case
Thermal Resistance
− Junction to Ambient
R
R
0.50
40
°
C/W
°
C
θ
JC
JA
θ
ORDERING INFORMATION
Maximum Lead
T
e
mperature for Soldering
T
260
L
Purposes, 1/8
″
from case for 10 seconds
Device
MTW24N40E
Package
Shipping
TO−247
30 Units/Rail
Preferred
devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
September, 2000 − Rev. XXX
MTW24N40E/D
MTW24N40E
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
(BR)DSS
(V =
0 Vdc, I
= 250
µ
Adc)
T
e
mperature Coefficient (Positive)
400
−
−
360
−
−
Vdc
mV/
°
C
GS
D
Zero Gate Voltage Drain Current
I
µ
Adc
DSS
GSS
(V =
400 Vdc, V
= 0 Vdc)
−
−
−
−
10
100
DS
GS
(V =
400 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
±
20 Vdc, V
= 0)
I
−
−
100
nAdc
GS
DS
Gate Threshold Voltage
(V =
V ,
I =
250
µ
Adc)
V
GS(th)
2.0
−
−
7.0
4.0
−
Vdc
mV/
°
C
DS
GS
D
T
e
mperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
= 10 Vdc, I
= 12 Adc)
R
V
−
0.13
0.16
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V
= 10 Vdc)
GS
DS(on)
(I =
24 Adc)
(I =
12 Adc, T
=125
°
C)
D
−
−
−
−
4.5
4.3
D
J
Forward Transconductance (V
= 15 Vdc, I
= 12 Adc)
g
FS
11
17
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
4000
530
112
5600
740
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
220
rss
Turn−On Delay Time
t
−
−
−
−
−
32
96
99
92
98
60
ns
d(on)
(V 200=
Vdc, I
= 24 Adc,
DD
D
Rise Time
t
r
204
194
186
160
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
d(off)
R
= 9.1
Ω
)
G
t
f
Gate Charge
Q
nC
T
(See Figure 8)
(V =
320 Vdc, I
= 24 Adc,
DS
D
Q
Q
Q
−
−
−
24
38
40
−
−
−
1
2
3
V
GS
= 10 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS
V
Vdc
ns
SD
(I =
24 Adc, V
= 0 Vdc)
S
GS
−
−
0.94
0.9
1.5
−
(I =
24 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
−
−
−
−
372
244
128
5.3
−
−
−
−
rr
t
a
(I =
24 Adc, V
= 0 Vdc,
S
GS
t
b
dI /dt
= 100 A/
µ
s)
S
Reverse Recovery Stored
Charge
Q
µ
C
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″
from package to center of die)
L
−
−
4.5
13
−
−
nH
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25
″
from package to source bond pad)
1. Pulse
T
e
st: Pulse Width
≤
300
µ
s, Duty Cycle
≤
2%.
2. Switching
characteristics are independent of operating junction temperature.
2
MTW24N40E
TYPICAL ELECTRICAL CHARACTERISTICS
50
40
30
20
10
0
50
V
DS
≥
10 V
T = 25
°
C
J
V
GS
= 10 V
40
30
20
10
0
9 V
8 V
7 V
6 V
5 V
4 V
25
°
C
100
°
C
T =
−
5
5
°
C
J
0
2.0
4.0
6.0
8.0
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.4
0.35
0.3
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
V
GS
= 10 V
T = 25
°
C
J
T = 100
°
C
J
0.25
0.2
V
GS
= 10 V
25
°
C
0.15
0.1
15 V
−
5
5
°
C
0.05
0
0
10
20
30
40
50
0
10
20
30
40
50
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
10000
1000
100
10
V
GS
= 0 V
V
= 10 V
T =
125
°
C
GS
J
I
D
= 12 A
100
°
C
25
°
C
1
−ꢀ50 −ꢀ25
0
25
50
75
100
125
150
0
100
200
300
400
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
3
MTW24N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
∆
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
9000
10000
C
iss
V
= 0 V
GS
T =
25
°
C
C
iss
T = 25
°
C
J
V
V
= 0 V
= 0 V
DS
8000
7000
6000
5000
4000
3000
2000
J
GS
1000
100
10
C
C
C
rss
iss
C
oss
C
rss
oss
1000
0
C
rss
5
0
5
10
15
20
25
10
10
100
V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
1000
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a.
Capacitance Variation
4
MTW24N40E
1000
600
12
10
8
QT
V
DD
= 200 V
I
D
= 24 A
500
400
V
GS
= 10 V
V
GS
T =
25
°
C
J
Q1
Q2
t
r
I
D
= 24 A
6
300
200
100
t
T =
25
°
C
J
f
t
d(off)
4
t
2
100
0
d(on)
V
DS
Q3
20
10
0
1
10
R ,
GATE RESISTANCE (OHMS)
100
0
40
60
80
100
Q , TOTAL CHARGE (nC)
T
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9.
Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
24
V
= 0 V
GS
T =
25
°
C
J
20
16
12
8
4
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90
0.95
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10
µ
s. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T
)/(R ).
energy at currents below rated continuous I
can safely be
J(MAX)
C
θ
JC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
assumed to equal the values indicated.
5
MTW24N40E
SAFE OPERATING AREA
100
10
700
600
500
400
300
200
V
=ꢁ20 V
GS
SINGLE PULSE
I
D
= 24 A
T
= 25
°
C
C
100
µ
s
1 ms
10 ms
DC
1.0
0.1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
100
0
0.1
1.0
10
100
1000
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
(pk)
0.01
R
θ
(t) = r(t) R
θ
JC
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
SINGLE PULSE
0.01
t
1
READ TIME AT t
1
t
2
T
− T
= P
C
R (t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13.
Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
MTW24N40E
PACKAGE DIMENSIONS
TO−247
CASE 340K−01
ISSUE C
−T−
E
−Q−
NOTES:
M
M
0.25 (0.010)
T B
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
−B−
C
4
U
L
MILLIMETERS
DIM MIN
MAX
INCHES
MIN
MAX
0.799
0.626
0.209
0.055
A
B
C
D
E
F
19.7
15.3
4.7
20.3 0.776
15.9 0.602
5.3 0.185
1.4 0.039
A
K
R
1.0
1
2
3
1.27 REF
2.0
5.5 BSC
0.050 REF
2.4 0.079
0.094
G
H
J
0.216 BSC
−Y−
2.2
0.4
2.6 0.087
0.8 0.016
14.8 0.559
0.102
0.031
0.583
P
K
L
14.2
5.5 NOM
0.217 NOM
P
Q
R
U
V
3.7
3.55
4.3 0.146
3.65 0.140
0.169
0.144
V
H
5.0 NOM
5.5 BSC
3.0
0.197 NOM
0.217 BSC
0.118 0.134
F
J
G
3.4
D
STYLE 1:
PIN 1.
GATE
2. DRAIN
M
S
Y Q
0.25 (0.010)
3. SOURCE
4. DRAIN
7
MTW24N40E
ON Semiconductor
and
are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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without further notice to any products herein.
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including without limitation special, consequential or incidental damages.
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MTW24N40E/D
