onsemi-MTY30N50E
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MTY30N50E
Preferred Device
Power MOSFET
30 Amps, 500 Volts
N−Channel TO−264
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced Power MOSFET is
designed to withstand high energy in the avalanche and commutation
modes. Designed for high voltage, high speed switching applications
in power supplies, converters and PWM motor controls, these devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
30 AMPERES
500 VOLTS
DS(on)
= 150 m
Ω
R
N−Channel
•
Robust High
V
o
ltage Termination
•
Avalanche Energy Specified
D
•
Diode is Characterized for Use in Bridge Circuits
•
I
and V
Specified at Elevated Temperature
DSS
DS(on)
G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
S
Rating
Drain−Source Voltage
Symbol
Value
500
Unit
Vdc
Vdc
V
V
DSS
Drain−Gate Voltage (R
= 1 M
Ω
)
500
TO−264
CASE 340G
Style 1
GS
DGR
Gate−Source Voltage
− Continuous
V
±
20
±
40
Vdc
Vpk
GS
V
GSM
1
− Non−Repetitive (t
≤
10 ms)
p
2
3
Drain Current − Continuous @ T
= 25
°
C
I
30
80
Adc
Apk
C
D
MARKING DIAGRAM
& PIN ASSIGNMENT
Drain Current
− Single Pulse (t
≤
10
µ
s)
I
DM
p
T
o
tal Power Dissipation
P
300
Watts
D
Derate above 25
°
C
2.38
W/
°
C
Operating and Storage
T
e
mperature Range
Single Pulse Drain−to−Source Avalanche
T , T
−
5
5 to
150
°
C
J
stg
MTY30N50E
LLYWW
E
AS
3000
mJ
Energy − Starting T
= 25
°
C
J
(V =
100 Vdc, V
= 10 Vdc, Peak
DD
GS
I =
30 Apk, L = 10 mH, R
= 25
Ω
)
L
G
1
Gate
3
Thermal Resistance − Junction to Case
Thermal Resistance
− Junction to Ambient
R
R
0.42
40
°
C/W
°
C
θ
JC
JA
Source
θ
2
Maximum Lead
T
e
mperature for Soldering
T
260
L
Drain
Purposes, 1/8
″
from case for 10 seconds
LL
Y
= Location Code
=
Y
e
ar
WW
= Work Week
ORDERING INFORMATION
Device
MTY30N50E
Package
Shipping
TO−264
25 Units/Rail
Preferred
devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
September, 2004 − Rev. XXX
MTY30N50E/D
MTY30N50E
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
(BR)DSS
(V =
0, I
= 250
µ
A)
T
e
mperature Coefficient (Positive)
500
−
−
566
−
−
Vdc
mV/
°
C
GS
D
Zero Gate Voltage Drain Current
I
µ
Adc
DSS
GSS
(V =
500 Vdc, V
= 0 Vdc)
−
−
−
−
10
200
DS
GS
(V =
500 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
±
20 Vdc, V
= 0)
I
−
−
100
nAdc
GS
DS
Gate Threshold Voltage
(V =
V ,
I =
250
µ
Adc)
V
GS(th)
2
−
−
7
4
−
Vdc
mV/
°
C
DS
GS
D
Threshold
T
e
mperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
= 10 Vdc, I
= 15 Adc)
R
V
−
−
0.15
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V
= 10 Vdc)
GS
DS(on)
(I =
30 Adc)
(I =
15 Adc, T
= 125
°
C)
D
−
−
4.1
−
5
7
D
J
Forward Transconductance (V
= 15 Vdc, I
= 15 Adc)
g
FS
17
−
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
7200
775
10080
1200
250
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1 MHz)
Reverse Transfer Capacitance
C
120
rss
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
32
105
160
115
235
35
60
175
275
200
350
−
ns
d(on)
(V =
250 Vdc, I
= 30 Adc,
DD
D
Rise Time
t
r
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
d(off)
R
= 4.7
Ω
)
G
t
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
(V =
400 Vdc, I
= 30 Adc,
DS
D
V
GS
= 10 Vdc)
110
65
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I =
30 Adc, V
= 0 Vdc)
S
GS
−
−
0.95
0.88
1.2
−
(I =
30 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
−
−
−
−
485
312
173
8.2
−
−
−
−
rr
t
a
(I =
30 Adc, V
= 0 Vdc,
S
GS
t
b
dI /dt
= 100 A/
µ
s)
S
Reverse Recovery Stored
Charge
Q
µ
C
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″
from package to center of die)
L
−
−
4.5
13
−
−
nH
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25
″
from package to source bond pad)
1. Pulse
T
e
st: Pulse Width
≤
300
µ
s, Duty Cycle
≤
2%.
2. Switching
characteristics are independent of operating junction temperature.
2
0
−
5
2
5
0
25
50
75
100
125
150
0
100
200
300
400
500
MTY30N50E
TYPICAL ELECTRICAL CHARACTERISTICS
60
50
40
30
20
10
60
V
GS
= 10 V
T =
25
°
C
6 V
V
≥
10 V
J
DS
50
40
30
20
10
0
8 V
5 V
100
°
C
T =
−ꢀ5
5
°
C
J
25
°
C
4 V
0
0
2
4
6
8
10
12
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.35
0.3
0.17
0.16
0.15
0.14
0.13
0.12
T =
25
°
C
J
V
GS
= 10 V
T
= 100
°
C
J
0.25
0.2
V
GS
= 10 V
25
°
C
0.15
0.1
15 V
−ꢀ5
5
°
C
0.05
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.5
2
10000
1000
100
T
= 125
°
C
100
°
C
J
V
I
= 10 V
GS
= 15 A
D
1.5
1
V
GS
= 0 V
25
°
C
10
1
0.5
0
−
T , JUNCTION TEMPERATURE (
°
C)
J
V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
3
MTY30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
∆
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
The capacitance (C
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
G
iss
GG GSP
24000
100000
V
DS
= 0 V
V
GS
= 0 V
V
GS
= 0 V
T =
25
°
C
J
T =
25
°
C
20000
16000
12000
8000
4000
0
J
C
iss
10000
1000
100
C
iss
C
rss
C
oss
C
iss
C
rss
C
oss
C
rss
10
10
5
0
5
10
15
20
25
10
100
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
V
GS
V
DS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a.
Capacitance Variation
4
MTY30N50E
12
10
8
600
500
400
300
200
10000
1000
100
V
= 250 V
DD
= 30 A
QT
I
D
V
GS
= 10 V
T =
25
°
C
J
V
GS
6
t
t
d(off)
Q2
Q1
t
f
T =
25
°
C
J
4
t
r
I
D
= 30 A
2
100
0
d(on)
V
DS
Q3
0
10
0
50
100
150
200
250
1
10
R ,
GATE RESISTANCE (OHMS)
100
Q ,
TOTAL GATE CHARGE (nC)
g
G
Figure 8. Gate Charge versus Gate−to−Source Voltage
Figure 9.
Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
30
V
GS
= 0 V
T =
25
°
C
J
20
10
0
0.5
0.55 0.6
0.65
0.7 0.75 0.8 0.85
0.9 0.95
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10
µ
s. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T
)/(R ).
energy at currents below rated continuous I
can safely be
J(MAX)
C
θ
JC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
assumed to equal the values indicated.
5
MTY30N50E
SAFE OPERATING AREA
100
10
1
3000
V
= 20 V
SINGLE PULSE
GS
2500
I =
30 A
D
10
µ
s
T
= 25
°
C
C
2000
1500
100
µ
s
1 ms
10 ms
1000
500
0
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
1000
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P
(pk)
0.05
R
θ
(t) = r(t) R
θ
JC
0.1
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.02
0.01
t
1
1
t
2
T
− T
= P
C
R (t)
θ
JC
SINGLE PULSE
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13.
Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
MTY30N50E
PACKAGE DIMENSIONS
TO−264
CASE 340G−02
ISSUE H
M
M
T B
0.25 (0.010)
−Q−
U
−T−
NOTES:
−B−
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
C
E
MILLIMETERS
DIM MIN
MAX
INCHES
MIN
N
MAX
1.142
0.800
0.209
0.058
0.083
0.102
A
B
C
D
E
F
28.0
19.3
4.7
0.93
1.9
29.0 1.102
20.3 0.760
5.3 0.185
1.48 0.037
2.1 0.075
2.4 0.087
A
L
1
2
3
R
2.2
−Y−
G
H
J
5.45 BSC
0.215 BSC
2.6
0.43
17.6
11.0
3.95
2.2
3.1
2.15
6.1
3.0 0.102
0.78 0.017
18.8 0.693
11.4 0.433
4.75 0.156
2.6 0.087
3.5 0.122
2.35 0.085
6.5 0.240
0.118
0.031
0.740
0.449
0.187
0.102
0.137
0.093
0.256
0.125
P
K
K
L
N
P
Q
R
U
W
W
F
2 PL
G
J
H
2.8
3.2
0.110
D
3 PL
M
S
Y Q
STYLE 1:
PIN 1.
GATE
2. DRAIN
3. SOURCE
0.25 (0.010)
7
MTY30N50E
ON Semiconductor
and
are trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes
without further notice to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time.
All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts.
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MTY30N50E/D
