onsemi-NCP348AEMTTBG
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NCP348, NCP348AE
Positive Overvoltage
Protection Controller with
Internal Low R
ON
NMOS FET
and Status FLAG
MARKING
The NCP348 is able to disconnect the systems from its output pin
in case wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28
V
.
Due to this device using internal NMOS, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
DIAGRAM
BAxM
G
WDFN10
MT SUFFIX
CASE 516AA
The NCP348 is able to instantaneously disconnect the output from
the input, due to integrated Low R
Power NMOS (65 m
W
), if the
ON
input voltage exceeds the overvoltage threshold (OVLO) or
undervoltage threshold (UVLO).
BAI =
NCP348
BAJ = NCP348AE
At powerup (
EN
pin = low level), the V
turns on 50 ms after the
out
M
= Date Code
V
in
exceeds the undervoltage threshold.
G
= Pb
−
Free Package
The NCP348 provides a negative going flag (
FLAG
) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD
−
protected input (15 kV Air) when
bypassed with a 1.0
m
F or larger capacitor.
PIN CONNECTIONS
IN
1
2
10 EN
Features
PAD1
GND
GND
9
NC
•
Overvoltage Protection up to 28 V
•
On
−
Chip Low R
NMOS Transistor: 65 m
W
DS(on)
FLAG
IN
3
4
5
8
7
6
NC
•
Internal Charge Pump
OUT
OUT
PAD2
IN
•
Overvoltage Lockout (OVLO)
•
Undervoltage Lockout (UVLO)
•
Internal 50 ms Startup Delay
•
Alert
FLAG
Output
IN
(
T
o
p View)
•
Shutdown
EN
Input
ORDERING INFORMATION
See detailed ordering and shipping information in the package
•
Compliance to IEC61000
−
4
−
2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
•
ESD Ratings: Machine Model = B
Human Body Model = 3
•
10 Lead WDFN 2.5×2 mm Package
•
This is a Pb
−
Free Device
Applications
•
Cell Phones
•
Camera Phones
•
Digital Still Cameras
•
Personal Digital Applications
•
MP3 Players
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
Ma
y
,
2
010
−
Rev. 6
NCP348/D
NCP348, NCP348AE
V
Bat
V
Bat
D3
70
1
1
X/SM
NCP1835B
ENABLE / Microprocessor
V2P8
6
7
9
10
3
2
EN
V2P8
VSNS
BAT
CFLG
FAULT
NCP348
V
Bat
Wall Adapter
−
AC/DC
1
m
F
1
4
5
1
6
7
8
IN
IN
IN
OUT
OUT
NC
V
CC
100 nF
ISEL
GND
5
4.7
m
F
9
8
4
10
NC
V
Lithium BATTERY
Bat
3
EN
270 K
FLAG
2
15 pF
ENABLE /
1 M
Microprocessor
0
0
Figure 1. Typical Application Circuit
INPUT
OUTPUT
60 mA
Output Impedance = 200 k
Core
Negative
Protection
FLAG
Gate
Driver
Charge
Pump
ESD
Protection
Delay
Generator
ESD
200 kHz
Protection
Power
ON
10 V
Oscillator
LDO
EN
EN
Block
V
REG
V
REG
UVLO
UVLO
OVLO
V
REF
OVLO
ESD
Protection
V
REF
V
REF
DISABLE
Figure 2. Functional Block Diagram
2
NCP348, NCP348AE
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
4
5
IN
POWER
Input Voltage Pin.
This pin is connected to the power supply.
The device system core is supplied by this input.
A 1
m
F low ESR ceramic capacitor, or larger, must be connected between this pin and GND.
The three IN pins must be hardwired to common supply.
2
3
GND
POWER
OUTPUT
Ground
FLAG
Fault Indication Pin.
This pin allows an external system to detect a fault on IN pin.
The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold.
Since the FLAG pin is open drain functionality, an external pull up resistor to V
must be added.
CC
6
7
OUT
OUTPUT
Output Voltage Pin.
This pin follows IN pin when “no fault” is detected.
The output is disconnected from the V
power supply when the input voltage is under the UVLO
in
threshold or above OVLO threshold.
The two OUT pins must be hardwired to common supply.
8
9
NC
NC
EN
OPEN
OPEN
INPUT
No Connect
No Connect
Enable Pin.
10
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To
a
llow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin.
This pin does not have an impact on the fault detection.
PAD1
PAD2
PAD1, under the device. See PCB recommendations page 10.
Can be shorted to GND.
The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5.
See PCB recommendations page 10.
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
−
0.3
Unit
V
Minimum Voltage (IN to GND)
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
Vmax
−
0.3
V
30
V
in
Maximum Voltage (All others to GND)
Vmax
Imax
R
7.0
V
Maximum Current (UVLO<V
<OVLO)
2.0
A
IN
Operating Ambient
T
e
mperature Range
Storage
T
e
mperature Range
280
°
C/W
°
C
°
C
°
C
q
JA
T
A
−
40 to +85
−
65 to +150
150
T
stg
Junction Operating
T
e
mperature
T
J
ESD Withstand Voltage (IEC 61000
−
4
−
2) (input only) when bypassed with 1.0
m
F capacitor
Vesd
15 Air, 8.0 Contact
kV
V
2000
200
V
Moisture Sensitivity
MSL
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommende
d
O
perating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
1. The
R
is highly dependent on the PCB heat sink area (connected to pad 2). As example R
is 268
°
C/W with 30 mm
(copper 35
m
m) and
q
JA
q
JA
2
189
°
C/W with 400 mm
.
2. Human
Body Model, 100 pF discharged through a 1.5 k
W
resistor following specification JESD22/A114.
3. Machine
Model, 200 pF discharged through all pins following specification JESD22/A115.
3
NCP348, NCP348AE
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (
−
40
°
C < T
< +85
°
C) and V
= +5.0
V
. Typical values are T
= +25
°
C,
A
in
A
unless otherwise noted.)
Characteristic
Symbol
Conditions
Min
1.2
3.0
20
Typ
−
Max
28
Unit
V
Input Voltage Range
V
in
−
−
−
Undervoltage Lockout Hysteresis
UVLO
UVLO
3.25
50
3.5
100
V
mV
V
hyst
OVLO
V
in
rises up OVLO threshold
NCP348MTT
NCP348AEMTT
6.0
5.7
6.4
6.02
6.8
6.4
Overvoltage Lockout Hysteresis
OVLO
−
mV
hyst
NCP348MTT
NCP348AEMTT
50
30
100
60
150
90
V
in
versus V
Resistance
R
DS(on)
V =
5.0
V
,
E
N = GND,
in
−
65
120
m
W
out
Load connected to V
out
Supply Quiescent Current
Idd
No load. EN = 5.0 V
No load. EN = Gnd
−
−
−
−
90
170
70
150
250
100
400
m
A
m
A
m
A
mV
UVLO Supply Current
Idd
V
IN
= 2.9 V
uvlo
FLAG
Output Low Voltage
Vol
1.2 V < V
< UVLO
20
flag
IN
Sink 50
m
A on/FLAG pin
V
IN
> OVLO
−
−
400
mV
Sink 1.0 mA on FLAG pin
FLAG
Leakage Current
EN
Voltage High
FLAG
FLAG level = 5.0 V
−
1.2
−
1.0
−
−
−
nA
V
leak
Vih
Vol
−
EN
Voltage Low
−
−
0.4
−
V
EN
Leakage Current
EN
EN = 5.0 V or GND
−
1.0
nA
leak
TIMINGS
Startup Delay
ton
From V
: (0 to (OVLO
−
300 mV)
30
55
70
ms
in
< V
< OVLO) to V
= 0.3 V
in
out
FLAG
Going Up Delay
tstart
toff
From V
= 0.3 V to FLAG = 1.2 V
30
50
70
ms
out
Output Turn Off Time
From V
> OVLO to V
< = 0.3 V
−
1.5
5.0
m
s
in
out
V
in
increasing from 5.0 V to 8.0 V at
3.0 V/
m
s, Rload connected on V
out
Alert Delay
tstop
tdis
From V
> OVLO to FLAG < = 0.4 V
−
−
1.0
1.0
−
m
s
m
s
in
V
in
increasing from 5.0 V to 8.0 V at
3.0 V/
m
s, Rload connected on V
out
Disable Time
From EN > = 1.2 V to V
< 0.3 V
5.0
out
Rload = 5.0
W
NOTE: Electrical
parameters are guaranteed by correlation across the full range of temperature.
4. Additional
UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representativ
e
f
or availability.
4
NCP348, NCP348AE
TIMING DIAGRAMS
<OVLO
OVLO
UVLO
V
in
V
V
in
t
off
V
out
t
on
V
in
−
(R
I)
DS(on)
V
−
(R
I)
in
DS(on)
0.3 V
0.3 V
out
t
start
FLAG
t
stop
1.2 V
FLAG
0.4 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
1.2 V
EN
1.2 V
EN
V
in
OVLO
UVLO
t
dis
V
out
V
in
−
(R
I)
DS(on)
FLAG
0.3 V
100 ms
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
5
NCP348, NCP348AE
TYPICAL OPERATING CHARACTERISTICS
Figure 7. Startup
V
in
= Ch1, V
out
= Ch3
Figure 8. Output Turn Off Time
V
in
= Ch1, V
out
= Ch2
Figure 9. FLAG Going Up Delay
V
out
= Ch3, FLAG = Ch2
Figure 10. Alert Delay
V
out
= Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
V
in
= Ch1, V
out
= Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, V
out
= Ch2, FLAG = Ch3
6
NCP348, NCP348AE
TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with C
out
= 100
m
F
,
Figure 14. Output Short Circuit
I charge = 1 A, Output Wall Adaptor Inductance 1
m
H
7
NCP348, NCP348AE
CONDITIONS
> OVLO
V
IN
IN
OUT
0 < V
< UVLO
IN
And/Or
/EN = 1
VOLTAGE DETECTION
Figure 16. Simplified Diagram
CONDITIONS
/EN = 0
&
IN
OUT
UVLO < V
< OVLO
IN
VOLTAGE DETECTION
Figure 17. Simplified Diagram
Operation
provides
a
FLAG
output, which alerts the system that a fault
has occurred. A 50 ms additional delay, regarding
rising up and to
FLAG
signal rising up.
FLAG
pin is an open
drain output.
The NCP348 provides overvoltage protection for
positive voltage, up to 28
V
. A
L
ow R
NMOS FET
protects the systems (i.e.: charger) connected on the
V
o
ut
pin, against positive overvoltage. At powerup, with
EN
pin
= low, the output is rising up 50 ms after the input
DS(on)
8
NCP348, NCP348AE
V
out
= 0
FLAG = Low
Reset Timer
V
in
V
in
< UVLO or
> OVLO
V
out
= 0
FLAG = Low
Timer Count
OVLO > V
> UVLO
in
T < 50 ms
Timer Check
T = 50 ms
Reset Timer
V
in
V
in
< UVLO or
> OVLO
Check V
in
FLAG = Low
Timer Count
UVLO < V
< OVLO
in
EN = 1
EN = 0
Check EN
V
out
= Open
V
= V
out in
V
in
V
in
< UVLO or
> OVLO
T < 50 ms
Timer Check
T = 50 ms
Check EN
UVLO < V
< OVLO
UVLO < V
< OVLO
in
in
EN = 1
EN = 0
V
= V
in
out
V
= Open
out
FLAG = High
Check V
FLAG = High
Check V
in
in
V
in
< UVLO or
V
in
> OVLO
Figure 18. State Machine
9
NCP348, NCP348AE
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built
−
in undervoltage lockout (UVLO) circuit.
As example: R
= 8.0
W
, V
= 5.0 V
in
load
Typical R
= 65 m
W,
I =
618 mA
DS(on)
out
V
out
= 8 x 0.618 = 4.95 V
During V
positive going slope, the output remains
in
2
2
NMOS losses = R
x Iout
= 0.065 x 0.618
= 25 mW
DS(on)
disconnected from input until V
voltage is below 3.25 V
in
(NCP348MTT version), plus hysteresis, nominal. The
ESD Tests
FLAG
output is tied to low as long as V
does not reach
in
The NCP348 input pin fully supports the IEC61000
−
4
−
2.
UVLO threshold. This circuit has a 50 mV hysteresis to
provide noise immunity to transient condition. Additional
UVLO thresholds ranging from UVLO can be
your ON Semiconductor representative for availability.
1.0
m
F (minimum) must be connected between V
and
GND, close to the device.
in
That means, in Air condition, V
has a
“
15 kV ESD
in
protected input. In Contact condition, V
has
“
8.0 kV
in
ESD protected input.
electrostatic discharge waveform.
Overvoltage Lockout (OVLO)
To protect connected systems on V
pin from
out
overvoltage, the device has a built
−
in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds 6.4 V
typical (NCP348MTT version). Additional OVLO
thresholds ranging from OVLO can be manufactured. (See
Selection Guide on page 12) Contact your ON
Semiconductor representative for availability.
FLAG
output is tied to low until V
is higher than OVLO.
in
This circuit has a 100 mV hysteresis to provide noise
immunity to transient conditions
.
FLAG
Output
The NCP348 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the V
level is below the UVLO
in
threshold. When V
level recovers normal condition,
in
Figure 19. Electrostatic Discharge Waveform
FLAG is held high, keeping in mind that an additional
50 ms delay has been added between available output and
FLAG = high. The pin is an open drain output, thus a pull
up resistor (typically 1 M
W
, minimum 10 k
W
) must be
PCB Recommendations
The NCP348 integrates a 2 amperes rated NMOS FET,
and the PCB rules must be respected to properly evacuate
the heat out of the silicon. The
P
A
D1 is internally isolated
from the active silicon and should preferably be connected
to ground. The
P
A
D2 of the NCP348 package is connected
to the internal NMOS drain and can be used to increase the
heat transfer if necessary from an applications standpoint.
Depending upon the power dissipated in the application,
one can either use the PCB tracks connected to Pins 4 and
5 to evacuate heat, or make profit of the
P
A
D2 area to add
extra copper surface to reduce the junction temperature
added to V
. Minimum V
supply must be 2.5
V
.
T
he
bat
bat
FLAG level will always reflects V
status, even if the
in
device is turned off (EN = 1).
EN
Input
To enable normal operation, the
EN
pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin.
EN
does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
The NCP348 includes an internal Low R
NMOS
DS(on)
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
area according to R
and allows the design of the heat
JA
q
transfer plane connected to
P
A
D2.
the R
, during normal operation, will create low losses
DS(on)
on V
pin.
out
10
NCP348, NCP348AE
310
290
270
250
230
1 oz C.
F
.
1 oz Sim
2 oz C.
F
.
2 oz Sim
1
2
210
190
175
150
0
25 50 75
100 12
5
1
5
0
1
75 20
0
2
25 25
0
2
75 300 325350
2
COPPER HEAT SPREADING AREA (mm
)
Figure 21. Demo Board Layout
Figure 20.
INPUT
OUTPUT
1
4
5
6
7
IN
IN
IN
OUT
OUT
C2
NCP348
C1
1
m
F 25 V X5R 0603
Murata GRM188R61E105KA12D
8
9
100 nF 50 V X7R 0805 not necessary
NC
NC
FLAG Power
3
10
FLAG
EN
FLAG
GND
2
EN_Power
EN_State
EN
R1
1 M
J2
1
R3
100 k
3 2
1
2
1
R2
GND
F1 F2 F3 F4
100 k
2
FLAG_State
Figure 22. Demo Board Schematic
11
NCP348, NCP348AE
ORDERING INFORMATION
Device
†
Package
Shipping
NCP348MTTBG
WDFN
−
10
(Pb
−
Free)
3000 /
T
a
pe & Reel
10000 /
T
a
pe & Reel
3000 /
T
a
pe & Reel
10000 /
T
a
pe & Reel
NCP348MTTXG
WDFN
−
10
(Pb
−
Free)
NCP348AEMTTBG
NCP348AEMTTXG
WDFN
−
10
(Pb
−
Free)
WDFN
−
10
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP348 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP348xxMTTxG
a b
c
Code
Contents
a
UVLO Typical Threshold
a:
−
= 3.25 V
a: A = 3.25 V
b
c
OVLO Typical Threshold
b:
−
= 6.4 V
b: E = 6.02 V
T
a
pe & Reel Type
c: B = 3000
c: X = 10000
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LLGA10 2.5×2.5, 0.5P
CASE 513AG-01
ISSUE A
DATE 15 MAY 2007
1
SCALE 4:1
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TI
P
.
4. COPLANARITY
APPLIES TO THE EXPOSED
PADS AS WELL AS THE TERMINALS.
A
D
B
E
PIN ONE
REFERENCE
2X
MILLIMETERS
0.10
C
DIM MIN
MAX
0.60
0.05
0.30
A
A1
b
D
D2
E
E2
e
G
K
L
0.50
0.00
0.20
2X
0.10
C
C
TOP VIEW
SIDE VIEW
2.50 BSC
0.90
1.00
A
2.50 BSC
0.05
1.45
1.55
0.50 BSC
0.20
0.20
0.30
—
0.05
C
11X
NOTE 4
A1
0.30 REF
0.05 BSC
0.20 0.30
SEATING
PLANE
L1
L3
C
(0.10)
GENERIC
MARKING DIAGRAM*
G
e
D2
2X
L1
10X
L
(0.10)
5
1
1
PIN ONE
DETAIL
XXXX
ALYW
G
E2
K
XXXX = Specific Device Code
AL
Y
= Assembly Location
=
Y
e
ar
10
0.10
0.05
C
C
A B
6
10X
L3
b
10X
W
G
= Work Week
= Pb-Free Package
NOTE 3
BOTTOM VIEW
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb-Free indicator, “G” or microdot “
G
”,
may or may not be present.
SOLDERING FOOTPRINT*
0.25
0.95
0.30
9X
2.90
1.50
1
10X
0.40
0.52
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mountin
g
T
e
chniques Reference Manual, SOLDERRM/D.
98AON24198D
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
D
E
S
C
R
I
P
T
ION: 10
PIN LLGA, 2.5X2.5, 0.5P
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON24198D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
A
RELEASED FOR PRODUCTION. REQ. BY W. CLEMENS.
ADDED DEVICE MARKING INFORMATION. REQ. BY W. CLEMENS.
09 MAR 2007
15 MAY 2007
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
©
ꢀ Semiconductor Components Industries, LLC, 2007
Ma
y
,
2
007 – Rev. 01A
Case Outline Number:
513AG
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN10 2.5×2, 0.5P
CASE 516AA
−
01
ISSUE C
DATE 06 FEB 2007
SCALE 4:1
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY
APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
E
PIN ONE
REFERENCE
MILLIMETERS
DIM
A
MIN
0.70
0.00
NOM
0.75
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
—
0.20 REF
0.25
0.20
0.30
2X
0.10
C
D
2.50 BSC
1.08
D2
D3
e
0.97
0.57
1.18
0.78
0.68
A3
0.50 BSC
2.00 BSC
0.90
0.10
C
E
E2
G
0.80
1.00
A
0.375 BSC
0.35 BSC
—
G1
K
10X
0.08
C
A1
0.20
0.20
—
L
0.30
0.40
SEATING
C
PLANE
GENERIC
MARKING DIAGRAM*
G1
0.10
0.05
C
A
B
D3
K
C
D2
XXXM
G
10X
L
1
5
XXX
M
= Specific Device Code
= Date Code
E2
G
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
10
6
8X
e
b
10X
0.10
0.05
C
C
A
B
G
0.10
0.05
C
A
B
NOTE 3
C
SOLDERING FOOTPRINT*
2.50
10X
0.58
0.95
10X
0.30
1.13
0.50
PITCH
0.05
0.73
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON21397D
WDFN10 2.5X2, 0.5P
PAGE 1 OF 1
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