onsemi-NJVMJB41CT4G

Part #onsemi-NJVMJB41CT4G
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onsemi-NJVMJB41CT4G
MJB41C,  
NJVMJB41CT4G (NPN),  
MJB42C,  
NJVMJB42CT4G (PNP)  
Complementary Silicon  
Plastic Power
T
r
ansistors  
D

2

PAK for Surface Mount  
Features  
COMPLEMENTARY SILICON  
POWER TRANSISTORS  
6 AMPERES,  
•
Lead Formed for Surface Mount Applications in Plastic Sleeves  
(No Suffix)  
•
Electrically the Same as TIP41 and T1P42 Series  
•
NJV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC
−
Q101  
Qualified and PPAP Capable  
•
Pb
−
Free Packages are Available  
100 VOLTS, 65 WATTS  
MARKING  
DIAGRAM  
2
D PAK  
J4xCG  
AYWW  
CASE 418B  
STYLE 1  
MAXIMUM RATINGS  
Rating  
Collector
−
Emitter Voltage  
Collector
−
Base Voltage  
Emitter
−
Base Voltage  
Symbol  
Value  
100  
100  
5.0  
Unit  
Vdc  
Vdc  
Vdc  
Adc  
V
CEO  
J4xC =
 
Specific Device Code  
x = 1 or 2  
V
CB  
EB  
A
Y
= Assembly
 
Location  
=
Y
e
ar  
V
WW =
 
Work Week  
Collector Current
 
−
Continuous  
−
Peak  
I
C
6.0  
10  
G
= Pb
−
Free Package  
Base Current  
I
B
2.0  
Adc  
ORDERING INFORMATION  
T
o
tal Power Dissipation  
P
D
†
Device  
Package  
Shipping  
@ T
 
= 25
_
C  
C
65  
0.52  
W
W/
_
C  
Derate above 25
_
C  
2
MJB41CG  
D PAK  
50 Units / Rail  
(Pb
−
Free)  
T
o
tal Power Dissipation  
P
D
@ T
 
= 25
_
C  
A
2.0  
W
2
MJB41CT4G  
NJVMJB41CT4G  
MJB42CG  
D PAK  
800 /
T
a
pe &  
Reel  
Derate above 25
_
C  
0.016  
W/
_
C  
mJ  
(Pb
−
Free)  
Unclamped Inductive Load Energy (Note

)  
E
62.5  
2
D PAK  
800 /
T
a
pe &  
Reel  
(Pb
−
Free)  
Operating and Storage Junction  
T
e
mperature Range  
T , T  
−
65 to +150  
_
C  
J
stg  
2
D PAK  
50 Units / Rail  
(Pb
−
Free)  
THERMAL CHARACTERISTICS  
Characteristic  
2
MJB42CT4G  
NJVMJB42CT4G  
D PAK  
800 /
T
a
pe &  
Reel  
Symbol  
Max  
1.92  
62.5  
Unit  
_
C/W  
_
C/W  
(Pb
−
Free)  
Thermal Resistance, Junction
−
to
−
Case  
R
q
JC  
2
D PAK  
800 /
T
a
pe &  
Reel  
Thermal Resistance,  
R
q
JA  
(Pb
−
Free)  
Junction
−
to
−
Ambient  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our
T
a
pe and Reel Packaging Specifications  
Brochure, BRD8011/D.  
Thermal Resistance,  
R
50  
_
C/W  
_
C  
q
JA  
Junction
−
to
−

Maximum Lead
T
e
mperature for Soldering  
Purposes, 1/8
″
from Case for 10 Seconds  
T
260  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. I
 
= 2.5 A, L = 20 mH,
P
.
R.
F
. =
1
0 Hz, V
 
= 10
V
, R
 
=
1
00
W
 
C
CC  
BE  
2. When
 
surface mounted to an FR
−
4 board using the minimum recommended  
pad size.  
©
Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013
−
Rev. 4  
MJB41C/D  
 

MJB41C, NJVMJB41CT4G (NPN), MJB42C, NJVMJB42CT4G (PNP)  
ELECTRICAL CHARACTERISTICS
(T =
 
25
_
C unless otherwise noted)  
C
Characteristic  
Symbol  
Min  
Max  
Unit  
OFF CHARACTERISTICS  
Collector
−
Emitter Sustaining Vo

= 30 mAdc, I
 
= 0)  
V
CEO(sus)  
100  
−
−
Vdc  
mAdc  
m
Adc  
m
Adc  
C
B
Collector Cutoff Current (V
 
= 60 Vdc, I
 
= 0)  
I
CEO  
0.7  
100  
50  
CE  
B
Collector Cutoff Current (V
 
= 100 Vdc, V
 
= 0)  
I
−
CE  
EB  
CES  
EBO  
Emitter Cutoff Current (V
 
= 5.0 Vdc, I
 
= 0)  
I
−
BE  
C
ON CHARACTERISTICS

DC Current Gain  
(I =
 
0.3 Adc, V
 
= 4.0 Vdc)  
h
FE  
30  
15  
−
75  
−
C
CE  
(I =
 
3.0 Adc, V
 
= 4.0 Vdc)  
C
CE  
Collector
−
Emitter Saturation Voltage (I
 
= 6.0 Adc, I
 
= 600 mAdc)  
V
CE(sat)  
−
−
1.5  
2.0  
Vdc  
Vdc  
C
B
Base
−
Emitter On Voltage (I
 
= 6.0 Adc, V
 
= 4.0 Vdc)  
V
BE(on)  
C
CE  
DYNAMIC CHARACTERISTICS  
Current
−
Gain
−
Bandwidth Product (I
 
= 500 mAdc, V
 
= 10 Vdc, f  
= 1.0 MHz)  
f
T
3.0  
20  
−
−
MHz  
C
CE  
test  
Small
−
Signal Current Gain (I
 
= 0.5 Adc, V
 
= 10 Vdc, f = 1.0 kHz)  
h
fe  
−
C
CE  
3. Pulse
 
T
e
st: Pulse Width
v
300
m
s, Duty Cycle
v
2.0%.  
T
A
T
C
4.0 80  
3.0 60  
2.0 40  
1.0 20  
T
C
T
A
0
0
0
20  
40  
60  
100  
120  
140  
160  
80  
T, TEMPERATURE (
°
C)  
Figure 1. Power Derating  
V
CC  
+ꢂ30 V  
2.0  
1.0  
T =
 
25
°
C  
J
R
V
CC  
I /I
 
= 10  
= 30 V  
25
m
s  
C
0.7  
0.5  
SCOPE  
+11 V  
0
C B  
R
B
0.3  
0.2  
t
r
-ꢂ9.0 V  
D
1
t , t
 
≤
10 ns  
0.1  
0.07  
0.05  
r
f
DUTY CYCLE = 1.0%  
t @
 
V  
d
≈
5.0 V  
-ꢂ4 V  
BE(off)  
R
and R
 
VARIED TO OBTAIN DESIRED CURRENT LEVELS  
C
B
0.03  
0.02  
D MUST
 
BE FAST RECOVERY TYPE, e.g.:  
1
ꢃꢃ1N5825 USED ABOVE I
 
≈
100 mA  
0.06 0.1  
0.2  
0.4 0.6  
1.0  
2.0  
4.0 6.0  
B
ꢃꢃMSD6100 USED BELOW I
 
≈
100 mA  
B
I ,
 
COLLECTOR CURRENT (AMP)  
C
Figure 2. Switching Time Test Circuit  
Figure 3. Turn
−
On Time  
2
 

MJB41C, NJVMJB41CT4G (NPN), MJB42C, NJVMJB42CT4G (PNP)  
1.0  
0.7  
0.5  
D = 0.5  
0.3  
0.2  
0.2  
0.1  
P
0.1  
0.07  
0.05  
(pk)  
Z
= r(t) R  
q
JC  
q
JC(t)  
0.05  
R
= 1.92
°
C/W MAX  
q
JC  
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
READ TIME AT t  
0.02  
0.01  
t
1
0.03  
0.02  
t
1
2
T
– T
 
= P  
C
Z
q
(pk) JC(t)  
J(pk)  
DUTY CYCLE, D = t
 
/t  
1 2  
SINGLE PULSE  
0.05  
0.01  
0.01  
0.02  
1.0  
0.2  
0.5  
1.0  
2.0  
5.0  
10  
20  
50  
100  
200  
500  
1.0 k  
t, TIME (ms)  
Figure 4. Thermal Response  
10  
There are two limitations on the power handling ability of  
a transistor: average junction temperature and second  
0.5ꢁms  
5.0  
breakdown. Safe operating area curves indicate I
 
−
V  
C
CE  
1.0ꢁms  
3.0  
2.0  
limits of the transistor that must be observed for reliable  
operation; i.e., the transistor must not be subjected to greater  
dissipation than the curves indicate.  
SECONDARY BREAKDOWN LTD  
BONDING WIRE LTD  
5.0ꢁms  
1.0  
0.5  
The data of Figure 5 is based on T  
variable depending on conditions. Second breakdown pulse  
= 150
_
C; T
 
is  
J(pk)  
C
THERMAL LIMITATION @ T
 
= 25
°
C  
C
(SINGLE PULSE)  
limits are valid for duty cycles to 10% provided T  
J(pk)  
CURVES APPLY BELOW RATED V  
CEO  
0.3  
0.2  
v
150
_
C.  
T
may be calculated from the data in  
J(pk)  
Figure 4. At high case temperatures, thermal limitations will  
reduce the power that can be handled to values less than the  
limitations imposed by second breakdown.  
0.1  
5.0  
10  
20  
40  
60  
80 100  
V
CE  
, COLLECTOR-EMITTER VOLTAGE (VOLTS)  
Figure 5. Active
−
Region Safe Operating Area  
5.0  
300  
T =
 
25
°
C  
J
3.0  
2.0  
T =
 
25
°
C  
J
200  
V
CC  
I /I
 
= 10  
= 30 V  
C B  
t
s
I =
 
I  
B1 B2  
1.0  
C
C
ib  
0.7  
0.5  
100  
70  
0.3  
0.2  
t
f
ob  
50  
0.1  
0.07  
0.05  
30  
0.06 0.1  
0.2  
0.4 0.6  
1.0  
2.0  
4.0 6.0  
0.5  
1.0  
2.0 3.0  
5.0  
10  
20 30  
50  
I ,
 
COLLECTOR CURRENT (AMP)  
C
V ,
 
REVERSE VOLTAGE (VOLTS)  
R
Figure 6. Turn
−
Off Time  
Figure 7. Capacitance  
3

MJB41C, NJVMJB41CT4G (NPN), MJB42C, NJVMJB42CT4G (PNP)  
500  
2.0  
T =
 
25
°
C  
300  
200  
J
V
CE  
= 2.0 V  
1.6  
1.2  
0.8  
0.4  
0
T =
 
150
°
C  
J
100  
70  
25
°
C  
I
C
= 1.0 A  
2.5 A  
5.0 A  
50  
30  
20  
-ꢂ55
°
C  
10  
7.0  
5.0  
0.06 0.1  
0.2 0.3
 
0.4 0.6  
1.0  
2.0  
4.0 6.0  
10  
20 30  
50  
100  
200 300
 
500  
1000  
I ,
 
COLLECTOR CURRENT (AMP)  
C
I ,
 
BASE CURRENT (mA)  
B
Figure 8. DC Current Gain  
Figure 9. Collector Saturation Region  
2.0  
1.6  
1.2  
0.8  
0.4  
0
+ꢂ2.5  
+ꢂ2.0  
+ꢂ1.5  
T =
 
25
°
C  
J
*APPLIES FOR I
 
/I
≤
h /4  
C B  
FE  
+ꢂ1.0  
+ꢂ0.5  
0
+ꢂ25
°
C to +ꢂ150
°
C  
*ꢂ
q
FOR V  
VC  
CE(sat)  
-ꢂ55
°
C to +ꢂ25
°
C  
+ꢂ25
°
C to +ꢂ150
°
C  
V
V
@ I
 
/I =
 
10  
C B  
BE(sat)  
-ꢂ0.5  
-ꢂ1.0  
-ꢂ1.5  
-ꢂ2.0  
-ꢂ2.5  
V
@ V
 
= 4.0 V  
CE  
BE  
q
FOR V  
BE  
VB  
-ꢂ55
°
C to +ꢂ25
°
C  
@ I
 
/I =
 
10  
C B  
CE(sat)  
0.06 0.1  
0.2 0.3
 
0.4 0.6  
1.0  
2.0 3.0 4.0
 
6.0  
0.06 0.1  
0.2 0.3  
0.5  
1.0  
2.0 3.0
 
4.0 6.0  
I ,
 
COLLECTOR CURRENT (AMP)  
C
I ,
 
COLLECTOR CURRENT (AMP)  
C
Figure 10. “On” Voltages  
Figure 11. Temperature Coefficients  
3
2
10  
10  
10  
10  
10ꢁM  
V
= 30 V  
CE  
V
CE  
= 30 V  
1.0ꢁM  
100ꢁk  
10ꢁk  
I
= 10 x I  
CES  
C
T =
 
150
°
C  
J
1
0
100
°
C  
I
C
≈
I  
CES  
25
°
C  
I
C
= I  
CES  
-1  
I
= 2 x I  
CES  
C
10  
10  
10  
1.0ꢁk  
0.1ꢁk  
-2  
REVERSE  
FORWARD  
(TYPICAL I
 
VALUES  
CES  
OBTAINED FROM FIGURE 12)  
-3  
-ꢂ0.3 -ꢂ0.2
 
-ꢂ0.1  
V
0
+ꢂ0.1 +ꢂ0.2 +ꢂ0.3 +ꢂ0.4 +ꢂ0.5 +ꢂ0.6
 
+ꢂ0.7  
20  
40  
60  
80  
100  
120  
140  
160  
, BASE-EMITTER VOLTAGE (VOLTS)  
T , JUNCTION TEMPERATURE (
°
C)  
BE  
J
Figure 12. Collector Cut
−
Off Region  
Figure 13. Effects of Base
−
Emitter Resistance  
4

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
D

2

PAK 3  
CASE 418B
−
04  
ISSUE L  
DATE 17 FEB 2015  
SCALE 1:1  
NOTES:  
1. DIMENSIONING
 
AND TOLERANCING  
PER ANSI Y14.5M, 1982.  
C
2. CONTROLLING
 
DIMENSION: INCH.  
3. 418B
−
01 THRU 418B
−
03 OBSOLETE,  
NEW STANDARD 418B
−
04.  
E
V
W
−
B
−  
INCHES  
DIM MIN
 
MAX  
MILLIMETERS  
4
MIN  
MAX  
A
B
C
D
E
F
G
H
J
0.340 0.380  
0.380 0.405  
0.160 0.190  
0.020 0.035  
0.045 0.055  
0.310 0.350  
0.100 BSC  
8.64  
9.65 10.29  
4.06  
0.51  
1.14  
7.87  
9.65  
4.83  
0.89  
1.40  
8.89  
A
S
1
2
3
2.54 BSC  
0.080  
0.018 0.025  
0.090 0.110  
0.110  
2.03  
0.46  
2.29  
1.32  
7.11  
5.00 REF  
2.00 REF  
0.99 REF  
2.79  
0.64  
2.79  
1.83  
8.13  
−
T
−  
SEATING  
PLANE  
K
W
J
K
L
G
0.052 0.072  
0.280 0.320  
0.197 REF  
0.079 REF  
0.039 REF  
0.575 0.625 14.60 15.88  
0.045 0.055  
M
N
P
R
S
V
H
D
3 PL  
M
M
T B  
0.13 (0.005)  
1.14  
1.40  
VARIABLE  
CONFIGURATION  
ZONE  
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W
−
W  
VIEW W
−
W  
VIEW W
−
W  
1
2
3
STYLE 1:  
STYLE 2:  
STYLE 3:  
STYLE 4:  
STYLE 5:  
PIN 1.
 
CATHODE  
2. ANODE  
STYLE 6:  
PIN 1.
 
NO CONNECT  
2. CATHODE  
PIN 1.
 
BASE  
PIN 1.
 
GATE  
PIN 1.
 
ANODE  
2. CATHODE  
3. ANODE  
PIN 1.
 
GATE  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
2. DRAIN  
3. SOURCE  
4. DRAIN  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
3. CATHODE  
4. ANODE  
3. ANODE  
4. CATHODE  
4. CATHODE  
MARKING INFORMATION AND FOOTPRINT ON PAGE 2  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42761B  
D

2

PAK 3  
PAGE 1 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

D

2

PAK 3  
CASE 418B
−
04  
ISSUE L  
DATE 17 FEB 2015  
GENERIC  
MARKING DIAGRAM*  
xx  
xxxxxxxxx  
AWLYWWG  
AYWW  
xxxxxxxxG  
AKA  
xxxxxxxxG  
AYWW  
IC  
Standard  
Rectifier  
xx  
A
WL  
Y
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
=
Y
e
ar  
WW  
G
AKA  
= Work Week  
= Pb
−
Free Package  
= Polarity Indicator  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”,  
may or may not be present.  
SOLDERING FOOTPRINT*  
10.49  
8.38  
16.155  
3.

2

5

X

04  
2X  
1.016  
5.080  
PITCH  
DIMENSIONS: MILLIMETERS  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42761B  
D

2

PAK 3  
PAGE 2 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

onsemi
,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates  
and/or subsidiaries in the United States and/or other countries.
onsemi
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onsemi
’s product/patent coverage may be accessed at

.
onsemi
reserves the right to make changes at any time to any  
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−
is” and
onsemi
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onsemi
assume any liability arising out of the application or use  
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