onsemi-NJVMJD44H11G
| Part # | onsemi-NJVMJD44H11G |
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DATA SHEET
Complementary Power
Transistors
SILICON
POWER TRANSISTORS
8 AMPERES
DPAK for Surface Mount Applications
80 VOLTS, 20 WATTS
MJD44H11ꢀ(NPN),
MJD45H11ꢀ(PNP)
COMPLEMENTARY
COLLECTOR
2, 4
COLLECTOR
2, 4
Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
1
1
BASE
BASE
Features
3
3
•
Lead Formed for Surface Mount Application in Plastic Sleeves
(No Suffix)
EMITTER
EMITTER
•
Straight Lead
V
e
rsion in Plastic Sleeves (“
−
1” Suffix)
4
•
Electrically Similar to Popular D44H/D45H Series
•
Low Collector Emitter Saturation
V
o
ltage
•
Fast Switching Speeds
4
4
1
•
Complementary Pairs Simplifies Designs
•
Epoxy Meets UL 94 V
−
0 @ 0.125 in
•
NJV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC
−
Q101
Qualified and PPAP Capable
2
1
1
2
2
3
3
3
DPAK
DPAK
IPAK
CASE 369C
STYLE 1
CASE 369G
STYLE 1
CASE 369D
STYLE 1
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
MARKING DIAGRAMS
Compliant
AYWW
J4
xH11G
AYWW
J4
xH11G
MAXIMUM RATINGS
(T =
25
_
C, common for NPN and PN
P
,
m
inus
A
sign, “
−
”, for PNP omitted, unless otherwise noted)
Rating
Symbol
Max
80
5
Unit
Vdc
Vdc
Adc
Adc
Collector
−
Emitter Voltage
Emitter
−
Base Voltage
V
CEO
DPAK
IPAK
A
Y
=
=
=
=
Assembly Location
Y
e
ar
Work Week
Device Code
x = 4 or 5
V
EB
Collector Current
−
Continuous
Collector Current
−
Peak
T
o
tal Power Dissipation
@ T
= 25
°
C
Derate above 25
°
C
I
C
8
WW
J4xH11
I
16
CM
P
D
20
0.16
W
W/
°
C
G
=
Pb
−
Free Package
C
P
D
1.75
0.014
W
W/
°
C
@ T
= 25
°
C
A
ORDERING INFORMATION
Derate above 25
°
C
See detailed ordering and shipping information in the package
Operating and Storage Junction
T
e
mperature Range
T , T
−
55 to
+
1
50
°
C
J
stg
ESD
−
Human Body Model
ESD
−
Machine Model
HBM
MM
3B
C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. These
ratings are applicable when surface mounted on the minimum pad
sizes recommended.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2021
−
Rev. 21
MJD44H11/D
MJD44H11 (NPN), MJD45H11 (PNP)
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
6.25
71.4
260
Unit
°
C/W
°
C/W
°
C
Thermal Resistance, Junction
−
to
−
Case
Lead
T
e
mperature for Soldering
R
q
JC
R
q
JA
T
L
2. These
ratings are applicable when surface mounted on the minimum pad sizes recommended.
ELECTRICAL CHARACTERISTICS
(T =
25
_
C, common for NPN and PN
P
,
m
inus sign, “
−
”, for PNP omitted, unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Collector
−
Emitter Sustaining Voltage
Symbol
Min
Typ
Max
Unit
V
Vdc
m
A
CEO(sus)
(I =
30 mA, I
= 0)
80
−
−
−
−
−
C
B
Collector Cutoff Current
(V =
Rated V
, V
= 0)
I
CES
1.0
1.0
CE
CEO BE
Emitter Cutoff Current
(V =
5 Vdc)
I
m
A
EBO
−
EB
ON CHARACTERISTICS
Collector
−
Emitter Saturation Voltage
V
V
Vdc
Vdc
−
CE(sat)
(I =
8 Adc, I
= 0.4 Adc)
−
−
−
−
1
C
B
Base
−
Emitter Saturation Voltage
(I =
8 Adc, I
= 0.8 Adc)
BE(sat)
1.5
C
B
DC Current Gain
(V =
1 Vdc, I
= 2 Adc)
h
FE
60
40
−
−
−
−
CE
C
(V =
1 Vdc, I
= 4 Adc)
CE
C
DYNAMIC CHARACTERISTICS
Collector Capacitance
C
pF
cb
(V =
10 Vdc, f
= 1 Mhz)
CB
test
MJD44H11
MJD45H11
−
−
45
130
−
−
Gain Bandwidth Product
(I =
0.5 Adc, V
= 10 Vdc, f = 20 Mhz)
f
T
MHz
C
CE
MJD44H11
MJD45H11
−
−
85
90
−
−
SWITCHING TIMES
Delay and Rise Times
t +
t
ns
ns
ns
d
r
(I =
5 Adc, I
= 0.5 Adc)
C
B1
MJD44H11
−
−
300
135
−
−
MJD45H11
Storage Time
t
s
(I =
5 Adc, I
= I
= 0.5 Adc)
C
B1
B2
MJD44H11
MJD45H11
−
−
500
500
−
−
Fall Time
(I =
5 Adc, I
= I
= 0.5 Adc)
t
f
C
B1
B2
MJD44H11
MJD45H11
−
−
140
100
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
MJD44H11 (NPN), MJD45H11 (PNP)
1
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
P
(pk)
R
R
= r(t) R
q
JC
q
q
JC(t)
= 6.25
°
C/W MAX
JC
0.1
0.07
0.05
0.05
0.02
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
1
READ TIME AT t
t
1
2
0.01
T
– T
= P
q
C (pk)
JC(t)
J(pk)
0.03
0.02
DUTY CYCLE, D = t
/t
1 2
SINGLE PULSE
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1
2
3
5
10
20 30
50
100
200 300
500
1 k
t, TIME (ms)
Figure 1. Thermal Response
20
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
100ꢀ
m
s
10
5
500ꢀ
m
s
breakdown. Safe operating area curves indicate I
−
V
C
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
1ꢀms
3
2
5ꢀms
dc
1
The data of Figure 2 is
based on T
variable depending on conditions. Second breakdown pulse
= 150
_
C; T
is
J(pk)
C
0.5
0.3
THERMAL LIMIT @ T
= 25
°
C
C
WIRE BOND LIMIT
limits are valid for duty cycles to 10% provided T
J(pk)
≤
150
_
C.
T
may be calculated from the data in
0.1
J(pk)
Figure 1.
At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
0.05
0.02
1
3
5
7
10
20 30
50 70
100
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 2. Maximum Forward Bias
Safe Operating Area
T
A
T
C
2.5 25
2
20
T
C
1.5 15
T
1
0.5
0
10
5
A
SURFACE
MOUNT
0
25
50
75
100
125
150
T, TEMPERATURE (
°
C)
Figure 3. Power Derating
3
MJD44H11 (NPN), MJD45H11 (PNP)
1000
100
1000
V
CE
= 1 V
V
CE
= 1 V
150
°
C
25
°
C
150
°
C
25
°
C
−
55
°
C
−
55
°
C
100
10
10
0.01
0.1
1
10
10
10
0.01
0.1
1
10
10
10
I ,
COLLECTOR CURRENT (A)
I ,
COLLECTOR CURRENT (A)
C
C
Figure 4. MJD44H11 DC Current Gain
Figure 5. MJD45H11 DC Current Gain
1000
1000
V
= 4 V
V
= 4 V
CE
CE
150
°
C
150
°
C
25
°
C
25
°
C
−
55
°
C
−
55
°
C
100
10
100
10
0.01
0.1
1
0.01
0.1
1
I ,
COLLECTOR CURRENT (A)
I ,
COLLECTOR CURRENT (A)
C
C
Figure 6. MJD44H11 DC Current Gain
Figure 7. MJD45H11 DC Current Gain
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
IC/IB = 20
IC/IB = 20
−
55
°
C
150
°
C
25
°
C
25
°
C
150
°
C
−
55
°
C
0.1
0
0.1
0
0.01
0.1
1
0.01
0.1
1
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 8. MJD44H11 Saturation Voltage
V
CE(sat)
Figure 9. MJD45H11 Saturation Voltage
V
CE(sat)
4
MJD44H11 (NPN), MJD45H11 (PNP)
1.4
1.2
1.0
0.8
0.6
0.4
1.4
1.2
1.0
−
55
°
C
25
°
C
−
55
°
C
0.8
25
°
C
0.6
150
°
C
150
°
C
0.4
IC/IB = 20
IC/IB = 20
0.2
0
0.2
0
0.01
0.1
1
10
0.01
0.1
1
10
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 10. MJD44H11 Saturation Voltage
V
BE(sat)
Figure 11. MJD45H11 Saturation Voltage
V
BE(sat)
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
T =
25
°
C
T =
25
°
C
A
A
I
C
= 8 A
I
C
= 8 A
I
C
= 3 A
I
C
= 3 A
1 A
1 A
10
I
= 0.1 A
0.5 A
1
0.2
0
0.2
0
0.5 A
C
I
C
= 0.1 A
0.1
100
1000
10,000
0.1
1
10
100
1000 10,000
I ,
BASE CURRENT (mA)
B
I ,
BASE CURRENT (mA)
B
Figure 12. MJD44H11 Collector Saturation
Region
Figure 13. MJD45H11 Collector Saturation
Region
1000
1000
Cob
Cob
100
10
100
10
0.1
1
10
100
0.1
1
10
100
V ,
REVERSE VOLTAGE (V)
R
V ,
REVERSE VOLTAGE (V)
R
Figure 14. MJD44H11 Capacitance
Figure 15. MJD45H11 Capacitance
5
MJD44H11 (NPN), MJD45H11 (PNP)
100
100
V
CE
= 2 V
V
CE
= 2 V
10
0.01
10
0.1
1
10
0.01
0.1
1
10
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 16. MJD44H11
Figure 17. MJD45H11
Current
−
Gain
−
Bandwidth Product
Current
−
Gain
−
Bandwidth Product
6
MJD44H11 (NPN), MJD45H11 (PNP)
ORDERING INFORMATION
Device
†
Package Type
Package
Shipping
MJD44H11G
DPAK
369C
75 Units / Rail
75 Units / Rail
(Pb
−
Free)
NJVMJD44H11G
MJD44H11
−
1G
DPAK
(Pb
−
Free)
369C
369D
369C
369C
369C
369C
369C
369C
369C
369D
369C
369C
369C
369C
369G
369G
DPAK
−
3
(Pb
−
Free)
75 Units / Rail
MJD44H11RLG
DPAK
(Pb
−
Free)
1,800 /
T
a
pe & Reel
1,800 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
75 Units / Rail
NJVMJD44H11RLG*
MJD44H11T4G
DPAK
(Pb
−
Free)
DPAK
(Pb
−
Free)
NJVMJD44H11T4G*
MJD44H11T5G
DPAK
(Pb
−
Free)
DPAK
(Pb
−
Free)
MJD45H11G
DPAK
(Pb
−
Free)
NJVMJD45H11G*
MJD45H11
−
1G
DPAK
(Pb
−
Free)
75 Units / Rail
DPAK
−
3
(Pb
−
Free)
75 Units / Rail
MJD45H11RLG
DPAK
(Pb
−
Free)
1,800 /
T
a
pe & Reel
1,800 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
2,500 /
T
a
pe & Reel
NJVMJD45H11RLG*
MJD45H11T4G
DPAK
(Pb
−
Free)
DPAK
(Pb
−
Free)
NJVMJD45H11T4G*
NJVMJD44H11D3T4G*
NJVMJD45H11D3T4G*
DPAK
(Pb
−
Free)
DPAK
(Pb
−
Free)
DPAK
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC
−
Q101 Qualified and PPAP
Capable
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D
−
01
ISSUE C
DATE 15 DEC 2010
C
B
NOTES:
SCALE 1:1
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
R
2. CONTROLLING
DIMENSION: INCH.
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
S
1
2
3
−
T
−
SEATING
PLANE
2.29 BSC
K
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D
3 PL
G
M
T
0.13 (0.005)
MARKING
DIAGRAMS
STYLE 1:
PIN 1.
BASE
STYLE 2:
STYLE 3:
PIN 1.
ANODE
STYLE 4:
PIN 1.
CATHODE
2. ANODE
Integrated
Circuits
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
Discrete
3. GATE
4. ANODE
xxxxx
ALYWW
x
YWW
xxxxxxxx
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
xxxxxxxxx =
Device Code
A
= Assembly Location
lL
Y
= Wafer Lot
=
Y
e
ar
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
D
E
C
A
b3
B
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
b2
0.028 0.045
b3
0.180 0.215
MILLIMETERS
L4
b2
e
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
BOTTOM VIEW
A
SIDE VIEW
b
b
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2
0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
PLANE
C
0.020 BSC
L3
0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−−
0.040
0.155
−−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 9
0
5
CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1.
BASE
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
PIN 1.
ANODE
STYLE 4:
STYLE 5:
PIN 1.
GATE
PIN 1.
CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
2. ANODE
3. CATHODE
4. ANODE
3. EMITTER
3. SOURCE
4. DRAIN
3. GATE
XXXXXXG
ALYWW
AYWW
XXX
4. COLLECTOR
4. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
STYLE 8:
PIN 1.
N/C
STYLE 9:
PIN 1.
ANODE
2. CATHODE
STYLE 10:
PIN 1.
CATHODE
2. ANODE
XXXXXG
PIN 1.
GATE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
3. ANODE
4. CATHODE
3. RESISTOR
ADJUST
4. CATHODE
3. CATHODE
4. ANODE
4. COLLECTOR
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX =
Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
=
Y
e
ar
= Work Week
= Pb
−
Free Package
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
onsemi
and
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
or its subsidiaries in the United States and/or other countries.
onsemi
reserves
the right to make changes without further notice to any products herein.
onsemi
makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does
onsemi
assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages.
onsemi
does not convey any license under its patent rights nor the rights of others.
©
Semiconductor Components Industries, LLC, 2018
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK
−
3, SURFACE MOUNT
CASE 369G
−
01
4
ISSUE O
1
2
3
DATE 23 DEC 2003
SCALE 1:1
SEATING
PLANE
−
T
−
NOTES:
C
B
R
1. DIMENSIONING
AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: INCH.
E
V
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
4
2
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
Z
A
K
1
3
U
4.58 BSC
0.87
0.46
2.60
1.01
0.58
2.89
F
J
L
K
L
G
2.29 BSC
H
R
U
V
Z
0.180 0.215
4.57
0.51
0.89
3.93
5.45
−−−
1.27
−−−
D
2 PL
0.020
0.035 0.050
0.155
−−−
−−−
0.13 (0.005)
T
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1.
BASE
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
STYLE 4:
PIN 1.
ANODE
2. CATHODE
3. ANODE
PIN 1.
CATHODE
2. ANODE
3. GATE
YWW
xxxxxxxx
2. COLLECTOR
3. EMITTER
4. COLLECTOR
3. SOURCE
4. DRAIN
4. CATHODE
4. ANODE
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
xxxxxxxxx =
Device Code
PIN 1.
GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
Y
=
Y
e
ar
3. CATHODE
4. ANODE
3. GATE
4. MT2
WW
= Work Week
*This information is generic. Please refer
to device data sheet for actual part
marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13702D
DPAK
−
3, SURFACE MOUNT
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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©
Semiconductor Components Industries, LLC, 2019
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onsemi
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Marking.pdf
.
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−
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