onsemi-NSB4904DW1T2G
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NSB4904DW1T1G,
NSB4904DW1T2G
Dual Bias Resistor
T
r
ansistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
6
5
4
R
R
2
The Bias Resistor Transistor (BRT) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base
−
emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSB4904DW1T1G and
NSB4904DW1T2G, two complementary BRT devices are housed in
the SC
−
88/SOT
−
363 package which is ideal for low power surface
mount applications where board space is at a premium.
1
Q
1
Q
2
R
2
R
1
1
2
3
1
Features
•
Simplifies Circuit Design
SC
−
88/SOT
−
363
CASE 419B
STYLE 1
•
Reduces Board Space
•
Reduces Component Count
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
6
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted, common for
A
Q and
Q ,
−
minus sign for Q
(PNP) omitted)
1
2
1
RC M
G
G
Rating
Symbol
Value
50
Unit
Vdc
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
V
V
CBO
CEO
1
50
Vdc
RC =
Device Marking
M
G
= Date Code
= Pb
−
Free Package
(Note: Microdot may be in either location)
I
C
100
mAdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See specific ordering information in the ordering information
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009
−
Rev. 2
NSB4904DW1T1G/D
NSB4904DW1T1G, NSB4904DW1T2G
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Max
Unit
T
o
tal Device Dissipation
P
mW
D
T =
25
°
C
A
Derate above 25
°
C
mW/
°
C
°
C/W
Thermal Resistance
−
Junction-to-Ambient
R
q
JA
Characteristic
(Both Junctions Heated)
Symbol
Max
Unit
T
o
tal Device Dissipation
P
mW
D
T =
25
°
C
A
Derate above 25
°
C
mW/
°
C
°
C/W
°
C/W
°
C
Thermal Resistance
−
Junction-to-Ambient
R
q
JA
Thermal Resistance
−
Junction-to-Lead
R
q
JL
Junction and Storage
T
e
mperature
T , T
J
−
55 to +150
stg
1. FR
−
4 @ Minimum Pad.
2. FR
−
4 @ 1.0 x 1.0 inch Pad.
2
NSB4904DW1T1G, NSB4904DW1T2G
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted, common for Q
and Q
,
−
minus sign for Q
(PNP) omitted)
A
1
2
1
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current (V
= 50 V, I
= 0)
I
I
−
−
−
−
−
−
−
100
500
0.1
−
nA
nA
mA
V
CB
E
CBO
Collector-Emitter Cutoff Current (V
= 50 V, I
= 0)
CE
B
CEO
Emitter-Base Cutoff Current (V
= 6.0 V, I
= 0)
I
EBO
−
EB
C
Collector-Base Breakdown Voltage (I
= 10
m
A, I
= 0)
V
V
50
50
C
E
(BR)CBO
(BR)CEO
−
V
C
B
DC Current Gain (V
= 10 V, I
= 5.0 mA)
h
FE
80
−
140
−
−
CE
C
Collector-Emitter Saturation Voltage (I
= 10 mA, I
= 0.3 mA)
V
CE(sat)
0.25
0.2
−
V
V
C
B
Output Voltage (on) (V
= 5.0 V, V
= 3.5 V, R
= 1.0 k
W)
V
−
−
CC
B
L
OL
Output Voltage (off) (V
= 5.0 V, V
= 0.5 V, R
= 1.0 k
W
)
V
4.9
32.9
0.8
−
V
CC
B
L
OH
Input Resistor
Resistor Ratio
R1
R1/R2
47
1.0
61.1
1.2
k
W
3. New
resistor combinations. Updated curves to follow in subsequent data sheets.
4. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2.0%.
300
250
200
150
100
R
q
= 490
°
C/W
50
0
JA
−
50
0
50
100
150
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 1. Derating Curve
ORDERING INFORMATION AND RESISTOR VALUES
†
Device
R1 (K)
R2 (K)
Package
Shipping
NSB4904DW1T1G
47
47
SOT
−
363
(Pb
−
Free)
3000/
T
a
pe & Reel
3000/
T
a
pe & Reel
NSB4904DW1T2G
47
47
SOT
−
363
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specification Brochure, BRD8011/D.
3
NSB4904DW1T1G, NSB4904DW1T2G
TYPICAL ELECTRICAL CHARACTERISTICS
−
NSB4904DW1T1G, NSB4904DW1T2G NPN TRANSISTOR
10
1000
100
10
V
= 10 V
CE
I /I
= 10
C B
T ꢀ=ꢀ75
°
C
A
1
25
°
C
-25
°
C
25
°
C
75
°
C
T ꢀ=ꢀ-25
°
C
A
0.1
0.01
0
20
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 2. V
CE(sat)
versus I
C
Figure 3. DC Current Gain
1
100
10
1
25
°
C
f = 1 MHz
I =
0 V
75
°
C
E
T ꢀ=ꢀ-25
°
C
A
0.8
T =
25
°
C
A
0.6
0.4
0.1
0.01
0.2
V
= 5 V
O
0.001
0
0
10
20
30
40
50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (VOLTS)
R
V ,
INPUT VOLTAGE (VOLTS)
in
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
100
V
= 0.2 V
O
T ꢀ=ꢀ-25
°
C
A
25
°
C
75
°
C
10
1
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage versus Output Current
4
NSB4904DW1T1G, NSB4904DW1T2G
TYPICAL ELECTRICAL CHARACTERISTICS
−
NSB4904DW1T1G, NSB4904DW1T2G PNP TRANSISTOR
1
1000
100
10
I /I
= 10
C B
T ꢀ=ꢀ75
°
C
A
T ꢀ=ꢀ-25
°
C
A
25
°
C
25
°
C
75
°
C
-25
°
C
ꢁ0.1
ꢁ0.01
0
10
20
30
40
1
10
I ,
COLLECTOR CURRENT (mA)
100
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 7. V
CE(sat)
versus I
C
Figure 8. DC Current Gain
1
100
25
°
C
-25
°
C
T ꢀ=ꢀ75
°
C
A
f = 1 MHz
l =
0 V
E
0.8
10
1
T =
25
°
C
A
0.6
0.4
ꢁ0.1
ꢁ0.01
0.2
0
V
= 5 V
ꢁ5
O
ꢁ0.001
0
10
20
30
40
50
0
1
2
3
ꢁ4
ꢁ6
ꢁ7
ꢁ8
ꢀ9
10
V ,
REVERSE BIAS VOLTAGE (VOLTS)
R
V ,
INPUT VOLTAGE (VOLTS)
in
Figure 9. Output Capacitance
Figure 10. Output Current versus Input Voltage
100
V
= 0.2 V
O
T ꢀ=ꢀ-25
°
C
A
25
°
C
75
°
C
10
1
ꢀ0.1
0
10
ꢁ20
ꢁ30
ꢁ40
ꢁ50
I ,
COLLECTOR CURRENT (mA)
C
Figure 11. Input Voltage versus Output Current
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
A
3. DIMENSIONS
D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS
D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS
A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS
b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TI
P
.
7. DIMENSION
b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM
MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOO
T
.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN
NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−−
0.043
−−−
0.004
6X
b
B
TOP VIEW
A
−−−
−−−
1.10
A1
0.00
A2
0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1
1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXM
G
6X
0.66
G
1
2.50
XXX =
Specific Device Code
M
= Date Code*
G
= Pb
−
Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1.
ANODE 2
2. N/C
PIN 1.
CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1.
ANODE
2. ANODE
3. COLLECTOR
1
4. EMITTER
1
5. BASE
1
3. COLLECTOR
3. CATHODE
1
4. ANODE
1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR
2
6. ANODE
6. CATHODE
6. CATHODE
2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1.
SOURCE 2
2. DRAIN
2
3. GATE
1
PIN 1.
EMITTER 2
2. EMITTER
1
3. COLLECTOR
1
4. BASE
1
PIN 1.
SOURCE 2
2. SOURCE
1
3. GATE
1
PIN 1.
CATHODE 2
2. CATHODE
2
3. ANODE
1
PIN 1.
ANODE 2
2. ANODE
2
3. CATHODE
1
4. ANODE
1
5. ANODE
1
6. CATHODE
2
4. SOURCE
1
5. DRAIN
1
6. GATE
2
4. DRAIN
1
5. DRAIN
2
6. GATE
2
4. CATHODE
1
5. CATHODE
1
6. ANODE
2
5. BASE
2
6. COLLECTOR
2
STYLE 13:
PIN 1.
ANODE
2. N/C
STYLE 14:
PIN 1.
VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1.
VIN1
2. VCC
PIN 1.
ANODE 1
2. ANODE
2
PIN 1.
BASE 1
2. EMITTER
2
3. COLLECTOR
2
4. BASE
2
PIN 1.
BASE 1
2. EMITTER
1
3. COLLECTOR
2
4. BASE
2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE
3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE
3
5. CATHODE
2
6. CATHODE
1
5. EMITTER
1
6. COLLECTOR
1
5. EMITTER
2
6. COLLECTOR
1
6. CATHODE
STYLE 19:
PIN 1.
I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1.
ANODE 1
2. N/C
STYLE 22:
PIN 1.
D1 (i)
2. GND
STYLE 23:
PIN 1.
Vn
2. CH1
3. Vp
STYLE 24:
PIN 1.
CATHODE
2. ANODE
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE
2
4. CATHODE
2
5. N/C
3. D2
(i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V
CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2
(c)
5. VBUS
6. D1
(c)
4. N/C
5. V
EN
5. CH2
6. N/C
6. V
REF
6. CATHODE
1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 27:
PIN 1.
BASE 2
2. BASE
1
STYLE 28:
PIN 1.
DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1.
ANODE
2. ANODE
PIN 1.
SOURCE 1
2. DRAIN
2
3. DRAIN
2
4. SOURCE
2
5. GATE
1
PIN 1.
BASE 1
2. CATHODE
3. COLLECTOR
2
4. BASE
2
3. DRAIN
2
4. SOURCE
2
5. GATE
2
3. COLLECTOR
1
4. EMITTER
1
5. EMITTER
2
6. COLLECTOR
2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR
1
6. DRAIN
1
6. DRAIN
1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
onsemi
,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
onsemi
reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as
−
is” and
onsemi
makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does
onsemi
assume any liability arising out of the application or use
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and applications using
onsemi
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provided by
onsemi
. “Typical” parameters which may be provided in
onsemi
data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
onsemi
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onsemi
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:
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−
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o
ll Free USA/Canada
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