onsemi-NSS40300MZ4T1G
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NSS40300MZ4
Bipolar Power
T
r
ansistors
40
V
,
3
.0 A, Low V
CE(sat)
PNP
T
r
ansistor
2
ON Semiconductor’s
e PowerEdge
family of low V
CE(sat)
transistors are surface mount devices featuring ultra low saturation
voltage (V
) and high current gain capability. These are designed
CE(sat)
PNP TRANSISTOR
3.0 AMPERES
40 VOLTS, 2.0 WATTS
for use in low voltage, high speed switching applications where
affordable efficient energy control is important.
Typical applications are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
C 2, 4
2
cluster. The high current gain allows e PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
B 1
E 3
Schematic
Features
•
Complement to NSS40301MZ4 Series
4
•
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
1
2
3
SOT−223
CASE 318E
STYLE 1
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
C
Rating
Symbol
Value
40
Unit
Vdc
Vdc
Vdc
Adc
Adc
Adc
W
AYW
40300
G
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
V
CEO
1
V
40
CB
EB
A
Y
W
= Assembly Location
Y
e
ar
= Work Week
V
6.0
1.0
3.0
5.0
Base Current − Continuous
Collector Current − Continuous
Collector Current − Peak
I
B
40300 =
Specific Device Code
I
C
G
= Pb−Free Package
I
CM
PIN ASSIGNMENT
T
o
tal Power Dissipation
P
D
2.0
0.80
D
A
4
D
A
C
Operating and Storage Junction
T
e
mperature Range
T , T
–
5
5 to
+
1
50
°
C
J
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Mounted
on 1” sq. (645 sq. mm) Collector pad on FR−4 bd material.
2. Mounted
on 0.012” sq. (7.6 sq. mm) Collector pad on FR−4 bd material.
B
1
C
2
E
3
T
o
p View Pinout
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
September, 2013 − Rev. 3
NSS40300MZ4/D
NSS40300MZ4
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction−to−Case
Junction−to−Ambient on 1” sq. (645 sq. mm) Collector pad on FR−4 bd material
Junction−to−Ambient on 0.012” sq. (7.6 sq. mm) Collector pad on FR−4 bd material
°
C/W
R
R
64
155
q
q
JA
JA
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8” from case for 5 seconds
T
L
260
°
C
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (I
= 10 mAdc, I
= 0 Adc)
V
CEO(sus)
40
6.0
−
−
−
−
−
−
Vdc
Vdc
C
B
Emitter−Base Voltage (I
= 50
m
Adc, I
= 0 Adc)
V
−
E
C
EBO
CBO
Collector Cutoff Current (V
= 40 Vdc)
I
100
100
nAdc
nAdc
CB
Emitter Cutoff Current (V
= 6.0 Vdc)
I
−
BE
EBO
Collector−Emitter Saturation Voltage
V
V
Vdc
CE(sat)
(I =
0.5 Adc, I
= 50 mAdc)
−
−
−
−
−
−
0.070
0.150
0.400
C
B
(I =
1.0 Adc, I
= 20 mAdc)
C
B
(I =
3.0 Adc, I
= 0.3 Adc)
C
B
Base−Emitter Saturation Voltage (I
= 1.0 Adc, I
= 0.1 Adc)
−
−
−
−
1.0
0.9
Vdc
Vdc
−
C
B
BE(sat)
Base−Emitter On Voltage (I
= 1.0 Adc, V
= 2.0 Vdc)
V
BE(on)
C
CE
DC Current Gain
(I =
0.5 Adc, V
= 1.0 Vdc)
h
FE
200
175
100
−
−
−
−
350
−
C
CE
(I =
1.0 Adc, V
= 1.0 Vdc)
C
CE
(I =
3.0 Adc, V
= 1.0 Vdc)
C
CE
DYNAMIC CHARACTERISTICS
Output Capacitance (V
= 10 Vdc, f = 1.0 MHz)
C
−
−
40
−
−
pF
pF
CB
ob
Input Capacitance (V
= 5.0 Vdc, f = 1.0 MHz)
C
130
EB
ib
f
T
MHz
(I =
500 mA, V
= 10
V
, F
=
1
.0 MHz)
−
160
−
C
CE
test
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. f =
|h |
•
f
T
FE
test
2.5
2.0
1.5
1.0
T
C
T
A
0.5
0
25
50
75
100
125
150
T , TEMPERATURE (
°
C)
J
Figure 1. Power Derating
2
NSS40300MZ4
TYPICAL CHARACTERISTICS
600
500
400
300
200
700
V
CE
= 4 V
V
CE
= 1 V
150
°
C
600
500
400
300
200
150
°
C
25
°
C
25
°
C
−40
°
C
−40
°
C
100
0
100
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
10
10
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 2. DC Current Gain
Figure 3. DC Current Gain
1
1
I /I
= 10
C
B
I /I
= 50
150
°
C
C
B
150
°
C
25
°
C
−40
°
C
0.1
25
°
C
−40
°
C
0.1
0.01
0.001
0.01
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 4. Collector−Emitter Saturation Voltage
Figure 5. Collector−Emitter Saturation Voltage
1
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
CE
= 2 V
I
C
= 2 A
−40
°
C
25
°
C
1 A
0.1
0.5 A
0.1 A
150
°
C
0.1
0
0.01
1.0E−04 1.0E−03
1.0E−02
1.0E−01
1.0E+00
0.001
0.01
0.1
1
I ,
BASE CURRENT (A)
B
I ,
COLLECTOR CURRENT (A)
C
Figure 6. Collector Saturation Region
Figure 7. V
BE(on)
Voltage
3
NSS40300MZ4
TYPICAL CHARACTERISTICS
1.2
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
I /I
= 10
I /I
= 50
C B
C
B
−40
°
C
25
°
C
−40
°
C
25
°
C
150
°
C
150
°
C
0.1
0
0.1
0
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 8. Base−Emitter Saturation Voltage
Figure 9. Base−Emitter Saturation Voltage
350
100
80
T =
25
°
C
J
J
f
= 1 MHz
300
250
200
150
100
test
f
60
40
20
0
50
0
0
1
2
3
4
5
6
0
5
10
15
20
25
30
35
V
EB
, EMITTER BASE VOLTAGE (V)
V
CB
, COLLECTOR BASE VOLTAGE (V)
Figure 10. Input Capacitance
Figure 11. Output Capacitance
200
10
1
T =
25
°
C
J
180
160
140
120
100
80
f
= 1 MHz
test
0.5 ms
V
CE
= 10 V
1 ms
10 ms
100 ms
0.1
60
40
20
0
0.01
0.001
0.01
0.1
1
1
10
100
I ,
COLLECTOR CURRENT (A)
C
V
CE
, COLLECTOR−EMITTER VOLTAGE (V)
Figure 12. Current−Gain Bandwidth Product
Figure 13. Safe Operating Area
4
NSS40300MZ4
ORDERING INFORMATION
Device
†
Package
Shipping
NSS40300MZ4T1G
SOT−223
(Pb−Free)
1,000 /
T
a
pe & Reel
1,000 /
T
a
pe & Reel
4,000 /
T
a
pe & Reel
NSV40300MZ4T1G*
NSS40300MZ4T3G
SOT−223
(Pb−Free)
SOT−223
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT
−
223 (TO
−
261)
CASE 318E
−
04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT
−
223 (TO
−
261)
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
SOT
−
223 (TO
−
261)
CASE 318E
−
04
ISSUE R
DATE 02 OCT 2018
STYLE 1:
PIN 1.
BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1.
ANODE
STYLE 3:
STYLE 4:
PIN 1.
SOURCE
STYLE 5:
PIN 1.
DRAIN
PIN 1.
GATE
2. DRAIN
2. CATHODE
3. NC
2. DRAIN
3. GATE
4. DRAIN
2. GATE
3. SOURCE
4. DRAIN
3. SOURCE
4. GATE
4. CATHODE
STYLE 6:
PIN 1.
RETURN
STYLE 7:
STYLE 8:
STYLE 9:
STYLE 10:
PIN 1.
ANODE 1
2. CATHODE
3. ANODE
2
CANCELLED
PIN 1.
INPUT
2. GROUND
3. LOGIC
PIN 1.
CATHODE
2. ANODE
2. INPUT
3. OUTPUT
4. INPUT
3. GATE
4. CATHODE
4. GROUND
4. ANODE
STYLE 11:
PIN 1.
MT 1
STYLE 12:
STYLE 13:
PIN 1.
INPUT
2. OUTPUT
3. NC
PIN 1.
GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. MT
2
3. GATE
4. MT
2
4. OUTPUT
GENERIC
MARKING DIAGRAM*
AYW
XXXXX
G
G
1
A
Y
= Assembly Location
=
Y
e
ar
W
= Work Week
XXXXX =
Specific Device Code
G
= Pb
−
Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT
−
223 (TO
−
261)
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
onsemi
,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
onsemi
reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as
−
is” and
onsemi
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onsemi
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provided by
onsemi
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onsemi
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
TECHNICAL SUPPORT
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−
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−
9855
T
o
ll Free USA/Canada
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