onsemi-NSV9435T1G
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NSB9435T1G,
NSV9435T1G
High Current Bias Resistor
Transistor
PNP Silicon
Features
Collector
−
Emitter Sustaining
V
o
ltage
−
POWER BJT
V
= 30 Vdc (Min) @ I
= 10 mAdc
CEO(sus)
C
I
C
= 3.0 AMPERES
BV
CEO
= 30 VOLTS
CE(sat)
= 0.275 VOLTS
High DC Current Gain
−
= 125 (Min) @ I
= 0.8 Adc
h
FE
C
V
= 90 (Min) @ I
= 3.0 Adc
C
Low Collector
−
Emitter Saturation
V
o
ltage
−
= 0.275 Vdc (Max) @ I
= 1.2 Adc
V
CE(sat)
C
= 0.55 Vdc (Max) @ I
= 3.0 Adc
C
SOT
−
223 Surface Mount Packaging
ESD Rating
−
Human Body Model: Class 1B
−
Machine Model: Class B
SOT
−
223
CASE 318E
STYLE 1
AEC
−
Q101 Qualified and P
P
A
P Capable
COLLECTOR 2, 4
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant*
BASE
1
EMITTER 3
MAXIMUM RATINGS
(T =
25
C unless otherwise noted)
C
Rating
Collector
−
Emitter Voltage
Collector
−
Base Voltage
Emitter
−
Base Voltage
Symbol
Value
30
Unit
Vdc
Vdc
Vdc
Adc
Adc
MARKING DIAGRAM
V
CEO
V
CB
45
AYW
9435R
G
G
V
EB
6.0
1.0
Base Current
−
Continuous
I
B
1
Collector Current
Continuous
Peak
I
C
3.0
5.0
A
Y
= Assembly Location
=
Y
e
ar
W
= Work Week
T
o
tal Power Dissipation
P
D
W
mW/
_
C
W
@ T
= 25
_
C
3.0
24
9435R =
Device Code
C
Derate above 25
_
C
G
= Pb
−
Free Package
1.56
T
o
tal P
@ T
= 25
_
C mounted on 1
sq.
D
A
(Note: Microdot may be in either location)
(645 sq. mm) Collector pad on FR
−
4 bd
material
W
0.72
T
o
tal P
@ T
= 25
_
C mounted on 0.012
D
A
ORDERING INFORMATION
sq. (7.6 sq. mm) Collector pad on FR
−
4 bd
†
material
Device
Package
Shipping
Operating and Storage Junction
T
e
mperature Range
T , T
–
5
5 to
+
1
50
_
C
NSB9435T1G
SOT
−
223 1,000/
T
a
pe
& Reel
(Pb
−
Free)
J
stg
NSV9435T1G
SOT
−
223 1,000/
T
a
pe
& Reel
(Pb
−
Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb
−
Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting
T
e
chniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
December, 2011
−
Rev. 7
NSB9435T1/D
NSB9435T1G, NSV9435T1G
THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
Unit
Thermal Resistance
_
C/W
Junction
−
to
−
Case
R
42
80
174
q
JC
JA
JA
Junction
−
to
−
Ambient on 1
sq. (645 sq. mm) Collector pad on FR
−
4 board material
Junction
−
to
−
Ambient on 0.012
sq. (7.6 sq. mm) Collector pad on FR
−
4 board material
R
q
R
q
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8
from case for 5 s
T
L
260
_
C
ELECTRICAL CHARACTERISTICS
(T
A
= 25
C unless otherwise noted)
Characteristics
OFF CHARACTERISTICS
Collector
−
Emitter Sustaining Voltage
Symbol
Min
Typ
Max
Unit
V
Vdc
Vdc
CEO(sus)
(I =
10 mAdc, I
= 0 Adc)
30
−
−
−
−
C
B
Emitter
−
Base Voltage
(I =
50
m
Adc, I
= 0 Adc)
V
EBO
6.0
E
C
Collector Cutoff Current
(V =
25 Vdc)
I
m
Adc
CER
−
−
−
−
20
200
CE
(V =
25 Vdc, T
= 125
C)
CE
J
Emitter Cutoff Current
I
m
Adc
EBO
(V =
5.0 Vdc)
−
−
700
BE
Collector
−
Emitter Saturation Voltage
V
V
Vdc
CE(sat)
(I =
0.8 Adc, I
= 20 mAdc)
−
−
−
0.155
−
−
0.210
0.275
0.550
C
B
(I =
1.2 Adc, I
= 20 mAdc)
C
B
(I =
3.0 Adc, I
= 0.3 Adc)
C
B
Base
−
Emitter Saturation Voltage
(I =
3.0 Adc, I
= 0.3 Adc)
Vdc
Vdc
−
BE(sat)
−
−
−
−
1.25
1.10
C
B
Base
−
Emitter On Voltage
V
BE(on)
(I =
1.2 Adc, V
= 4.0 Vdc)
C
CE
DC Current Gain
h
FE
(I =
0.8 Adc, V
= 1.0 Vdc)
125
110
90
220
−
−
−
−
−
C
CE
(I =
1.2 Adc, V
= 1.0 Vdc)
C
CE
(I =
3.0 Adc, V
= 1.0 Vdc)
C
CE
Resistor
R1
7.5
10
12.5
k
W
DYNAMIC CHARACTERISTICS
Output Capacitance
C
pF
pF
ob
(V =
10 Vdc, I
= 0 Adc, f = 1.0 MHz)
−
−
−
100
135
110
150
−
CB
E
Input Capacitance
C
ib
(V =
8.0 Vdc)
EB
(I =
500 mA, V
= 10
V
, F
=
1
.0 MHz)
f
T
MHz
−
C
CE
test
1. Pulse
T
e
st: Pulse Width
300
m
s, Duty Cycle
2%.
2. f =
|h |
S
f
T
FE
test
2
NSB9435T1G, NSV9435T1G
0.3
1000
0.25
0.2
I
C
= 3.0 A
T =
150
C
A
25
C
0.15
0.1
100
10
−
55
C
1.2 A
0.8 A
0.5 A
0.25 A
0.05
0
V
CE
= 1.0 V
0.001
0.01
0.1
1
0.1
1
10
I ,
BASE CURRENT (mA)
B
I ,
COLLECTOR CURRENT (A)
C
Figure 1. Collector Saturation Region
Figure 2. DC Current Gain
1000
10
1
T =
150
C
A
V
BE(sat)
25
C
100
10
−
55
C
V
CE(sat)
0.1
V
CE
= 4.0 V
I /I
= 10
C B
0.01
0.1
1
10
1.0E
−
01
1.0E+00
1.0E+01
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 3. DC Current Gain
Figure 4. “ON” Voltages
1.0E+00
1.2
V
V
BE(sat)
1
−
55
C
25
C
CE(sat)
0.8
0.6
0.4
T =
155
C
A
1.0E
−
01
1.0E
−
02
0.2
0
I /I
= 50
C
B
1.0E
−
01
1.0E+00
1.0E+01
0.1
1
10
I ,
COLLECTOR CURRENT (A)
C
I ,
COLLECTOR CURRENT (A)
C
Figure 5. “ON” Voltages
Figure 6. V
BE(on)
Voltage
3
NSB9435T1G, NSV9435T1G
1000
100
10
0.5 ms
5.0 ms
1.0
0.1
100 ms
10
1
0.01
BONDING WIRE LIMIT
THERMAL LIMIT (Single Pulse)
SECONDARY BREAKDOWN LIMIT
f = 1 MHz
T =
25
C
A
0.001
0.1
1
10
100
0.1
1.0
, COLLECTOR
−
EMITTER VOLTAGE (VOLTS)
CE
10
100
V ,
REVERSE VOLTAGE (V)
V
R
Figure 7. Output Capacitance
Figure 8. Active Region Safe Operating Area
4.0
3.0
2.0
There are two limitations on the power handling ability of
a transistor: average junction temperature and secondary
breakdown. Safe operating area curves indicate I
−
V
C
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
T
C
variable depending on conditions. Secondary breakdown
= 150
_
C; T
is
J(pk)
C
pulse limits are valid for duty cycles to 10% provided T
J(pk)
1.0
0
v
150
_
C. T
may be calculated from the data in
J(pk)
will reduce the power that can be handled to values less than
the limitations imposed by secondary breakdown.
T
A
25
50
75
100
125
150
T,
T
EMPERATURE (
C)
Figure 9. Power Derating
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
(pk)
0.01
R
(t) = r(t)
q
JA
q
JA
q
= 174
C/W
JA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
SINGLE PULSE
0.001
t
1
0.001
t
1
2
T
– T
= P
q
(t)
A (pk)
JA
J(pk)
DUTY CYCLE, D = t
/t
1 2
0.0001
0.0001
0.01
0.1
t, TIME (seconds)
1.0
10
100
1000
Figure 10. Thermal Response
4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT
−
223 (TO
−
261)
CASE 318E
−
04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT
−
223 (TO
−
261)
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
SOT
−
223 (TO
−
261)
CASE 318E
−
04
ISSUE R
DATE 02 OCT 2018
STYLE 1:
PIN 1.
BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1.
ANODE
STYLE 3:
STYLE 4:
PIN 1.
SOURCE
STYLE 5:
PIN 1.
DRAIN
PIN 1.
GATE
2. DRAIN
2. CATHODE
3. NC
2. DRAIN
3. GATE
4. DRAIN
2. GATE
3. SOURCE
4. DRAIN
3. SOURCE
4. GATE
4. CATHODE
STYLE 6:
PIN 1.
RETURN
STYLE 7:
STYLE 8:
STYLE 9:
STYLE 10:
PIN 1.
ANODE 1
2. CATHODE
3. ANODE
2
CANCELLED
PIN 1.
INPUT
2. GROUND
3. LOGIC
PIN 1.
CATHODE
2. ANODE
2. INPUT
3. OUTPUT
4. INPUT
3. GATE
4. CATHODE
4. GROUND
4. ANODE
STYLE 11:
PIN 1.
MT 1
STYLE 12:
STYLE 13:
PIN 1.
INPUT
2. OUTPUT
3. NC
PIN 1.
GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. MT
2
3. GATE
4. MT
2
4. OUTPUT
GENERIC
MARKING DIAGRAM*
AYW
XXXXX
G
G
1
A
Y
= Assembly Location
=
Y
e
ar
W
= Work Week
XXXXX =
Specific Device Code
G
= Pb
−
Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT
−
223 (TO
−
261)
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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:
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