onsemi-NSVBC143TPDXV6T1G
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MUN5316DW1,
NSBC143TPDXV6
Complementary Bias
Resistor
T
r
ansistors
R1 = 4.7 k
W
, R2 =
8
k
W
PIN CONNECTIONS
(2)
NPN and PNP Transistors with Monolithic
Bias Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
(3)
(1)
R
1
R
2
Q
1
Q
2
R
2
R
1
Features
•
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
(4)
(5)
(6)
•
Simplifies Circuit Design
MARKING DIAGRAMS
•
Reduces Board Space
•
Reduces Component Count
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
6
SOT−363
CASE 419B
16 M
G
G
1
1
MAXIMUM RATINGS
(T =
25
°
C both polarities Q1 (PNP) and Q2 (NPN), unless otherwise noted)
A
SOT−563
CASE 463A
Rating
Collector−Base Voltage
Collector−Emitter Voltage
Collector Current − Continuous
Input Forward Voltage
Symbol
Max
50
Unit
Vdc
16 M
G
V
CBO
G
V
CEO
50
Vdc
I
C
100
30
mAdc
Vdc
16
M
G
=
=
=
Specific Device Code
Date Code*
Pb−Free Package
V
IN(fwd)
Input Reverse Voltage
−NPN
−PNP
V
IN(rev)
Vdc
(Note: Microdot may be in either location)
6
5
*Date Code orientation may vary depending up-
on manufacturing location.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
†
Device
Package
Shipping
MUN5316DW1T1G
SOT−363
3,000 /
T
a
pe & Reel
NSVMUN5316DW1T1G*
NSBC143TPDXV6T1G,
NSVBC143TPDXV6T1G*
SOT−563
4,000 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
March, 2016 − Rev. 3
DTC143TP/D
MUN5316DW1, NSBC143TPDXV6
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
MUN5316DW1 (SOT−363) One Junction Heated
T
o
tal Device Dissipation
P
D
T =
25
°
C
187
256
1.5
2.0
mW
A
Derate above 25
°
C
mW/
°
C
Thermal Resistance,
Junction to Ambient
R
670
490
°
C/W
q
JA
T
o
tal Device Dissipation
P
D
T =
25
°
C
250
385
2.0
3.0
mW
A
Derate above 25
°
C
mW/
°
C
Thermal Resistance,
Junction to Ambient
R
493
325
°
C/W
°
C/W
°
C
q
JA
Thermal Resistance,
R
188
208
q
JL
Junction and Storage
T
e
mperature Range
NSBC143TPDXV6 (SOT−563) One Junction Heated
T
o
tal Device Dissipation
T , T
J
−55 to +150
stg
P
D
T =
25
°
C
Derate above 25
°
C
357
2.9
mW
mW/
°
C
A
Thermal Resistance,
Junction to Ambient
R
°
C/W
q
JA
D
350
T
o
tal Device Dissipation
P
T =
25
°
C
Derate above 25
°
C
500
4.0
mW
mW/
°
C
A
Thermal Resistance,
Junction to Ambient
R
°
C/W
q
JA
250
Junction and Storage
T
e
mperature Range
T , T
−55 to +150
°
C
J
stg
1. FR−4
@ Minimum Pad.
2. FR−4
@ 1.0 x 1.0 Inch Pad.
3. Both
junction heated values assume total power is sum of two equally powered channels.
2
MUN5316DW1, NSBC143TPDXV6
ELECTRICAL CHARACTERISTICS
(T =
25
°
C both polarities Q
(PNP) and Q
(NPN), unless otherwise noted)
A
1
2
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Base Cutoff Current
I
I
nAdc
nAdc
mAdc
Vdc
CBO
(V =
50
V
, I
=
0
)
−
−
−
−
−
−
−
100
500
1.9
−
CB
E
Collector−Emitter Cutoff Current
(V =
50
V
, I
=
0
)
CEO
CE
B
Emitter−Base Cutoff Current
(V =
6.0
V
, I
=
0
)
I
EBO
−
EB
C
Collector−Base Breakdown Voltage
(I =
10
m
A, I
= 0)
V
V
(BR)CBO
(BR)CEO
50
50
C
E
(I =
2.0 mA, I
= 0)
Vdc
−
C
B
ON CHARACTERISTICS
h
FE
(I =
5.0 mA, V
= 10 V)
160
−
350
−
−
0.25
−
C
CE
(I =
10 mA, I
= 0.3 mA)
V
Vdc
Vdc
CE(sat)
C
B
Input Voltage (off)
(V =
5.0
V
, I
=
1
00
m
A) (NPN)
V
i(off)
i(on)
−
0.6
0.58
CE
C
(V =
5.0
V
, I
=
1
00
m
A) (PNP)
CE
C
Input Voltage (on)
(V =
0.2
V
, I
=
1
0 mA) (NPN)
V
Vdc
−
−
0.9
1.0
−
CE
C
(V =
0.2
V
, I
=
1
0 mA) (PNP)
CE
C
Output Voltage (on)
(V =
5.0
V
, V
=
2
.5
V
, R
=
1
.0 k
W
)
V
OL
Vdc
Vdc
k
W
−
0.2
CC
B
L
Output Voltage (off)
V
OH
(V =
5.0
V
, V
=
0
.5
V
, R
=
1
.0 k
W
)
4.9
3.3
−
−
4.7
−
−
6.1
−
CC
B
L
Input Resistor
Resistor Ratio
R1
R /R
1
2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulsed
Condition: Pulse Width = 300 msec, Duty Cycle
≤
2%.
400
350
300
(1) SOT−363; 1.0 x 1.0 inch Pad
250
200
150
100
(2) SOT−563; Minimum Pad
(1) (2)
50
0
−50 −25
0
25
50
75
100
125 150
AMBIENT TEMPERATURE (
°
C)
Figure 1. Derating Curve
3
MUN5316DW1, NSBC143TPDXV6
TYPICAL CHARACTERISTICS − NPN TRANSISTORS
MUN5316DW1, NSBC143TPDXV6
1
1000
150
°
C
I /I
= 10
C
B
25
°
C
100
−55
°
C
150
°
C
25
°
C
0.1
10
1
−55
°
C
V
CE
= 10 V
0.01
0
10
20
30
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 2. V
CE(sat)
vs. I
C
Figure 3. DC Current Gain
3.2
2.8
2.4
100
10
1
150
°
C
f = 10 kHz
= 0 A
T =
25
°
C
A
25
°
C
−55
°
C
I
E
2.0
1.6
1.2
0.8
0.1
0.4
0
V
O
= 5 V
0.01
0
10
20
30
40
50
0
1
2
3
4
V ,
REVERSE VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 4. Output Capacitance
Figure 5. Output Current vs. Input Voltage
100
10
25
°
C
−55
°
C
1
150
°
C
V
O
= 0.2 V
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage vs. Output Current
4
MUN5316DW1, NSBC143TPDXV6
TYPICAL CHARACTERISTICS − PNP TRANSISTORS
MUN5316DW1, NSBC143TPDXV6
1
1000
I /I
= 10
150
°
C
C
B
25
°
C
100
−55
°
C
0.1
150
°
C
10
1
25
°
C
−55
°
C
V
CE
= 10 V
0.01
0
20
30
40
50
1
10
100
10
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 7. V
CE(sat)
vs. I
C
Figure 8. DC Current Gain
10
100
10
1
25
°
C
150
°
C
f = 10 kHz
= 0 A
T =
25
°
C
A
9
8
7
6
5
4
3
−55
°
C
l
E
0.1
2
1
0
0.01
V
O
= 5 V
0.001
0
10
20
30
40
50
0
1
2
3
4
5
V ,
REVERSE VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 9. Output Capacitance
Figure 10. Output Current vs. Input Voltage
100
V
O
= 0.2 V
25
°
C
10
−55
°
C
1
150
°
C
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 11. Input Voltage vs. Output Current
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
A
3. DIMENSIONS
D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS
D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS
A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS
b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TI
P
.
7. DIMENSION
b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM
MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOO
T
.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN
NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−−
0.043
−−−
0.004
6X
b
B
TOP VIEW
A
−−−
−−−
1.10
A1
0.00
A2
0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1
1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXM
G
6X
0.66
G
1
2.50
XXX =
Specific Device Code
M
= Date Code*
G
= Pb
−
Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1.
ANODE 2
2. N/C
PIN 1.
CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1.
ANODE
2. ANODE
3. COLLECTOR
1
4. EMITTER
1
5. BASE
1
3. COLLECTOR
3. CATHODE
1
4. ANODE
1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR
2
6. ANODE
6. CATHODE
6. CATHODE
2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1.
SOURCE 2
2. DRAIN
2
3. GATE
1
PIN 1.
EMITTER 2
2. EMITTER
1
3. COLLECTOR
1
4. BASE
1
PIN 1.
SOURCE 2
2. SOURCE
1
3. GATE
1
PIN 1.
CATHODE 2
2. CATHODE
2
3. ANODE
1
PIN 1.
ANODE 2
2. ANODE
2
3. CATHODE
1
4. ANODE
1
5. ANODE
1
6. CATHODE
2
4. SOURCE
1
5. DRAIN
1
6. GATE
2
4. DRAIN
1
5. DRAIN
2
6. GATE
2
4. CATHODE
1
5. CATHODE
1
6. ANODE
2
5. BASE
2
6. COLLECTOR
2
STYLE 13:
PIN 1.
ANODE
2. N/C
STYLE 14:
PIN 1.
VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1.
VIN1
2. VCC
PIN 1.
ANODE 1
2. ANODE
2
PIN 1.
BASE 1
2. EMITTER
2
3. COLLECTOR
2
4. BASE
2
PIN 1.
BASE 1
2. EMITTER
1
3. COLLECTOR
2
4. BASE
2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE
3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE
3
5. CATHODE
2
6. CATHODE
1
5. EMITTER
1
6. COLLECTOR
1
5. EMITTER
2
6. COLLECTOR
1
6. CATHODE
STYLE 19:
PIN 1.
I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1.
ANODE 1
2. N/C
STYLE 22:
PIN 1.
D1 (i)
2. GND
STYLE 23:
PIN 1.
Vn
2. CH1
3. Vp
STYLE 24:
PIN 1.
CATHODE
2. ANODE
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE
2
4. CATHODE
2
5. N/C
3. D2
(i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V
CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2
(c)
5. VBUS
6. D1
(c)
4. N/C
5. V
EN
5. CH2
6. N/C
6. V
REF
6. CATHODE
1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 27:
PIN 1.
BASE 2
2. BASE
1
STYLE 28:
PIN 1.
DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1.
ANODE
2. ANODE
PIN 1.
SOURCE 1
2. DRAIN
2
3. DRAIN
2
4. SOURCE
2
5. GATE
1
PIN 1.
BASE 1
2. CATHODE
3. COLLECTOR
2
4. BASE
2
3. DRAIN
2
4. SOURCE
2
5. GATE
2
3. COLLECTOR
1
4. EMITTER
1
5. EMITTER
2
6. COLLECTOR
2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR
1
6. DRAIN
1
6. DRAIN
1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT
−
563, 6 LEAD
CASE 463A
6
ISSUE H
1
DATE 26 JAN 2021
SCALE 4:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11126D
SOT
−
563, 6 LEAD
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
SOT
−
563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
GENERIC
MARKING DIAGRAM*
XX M
G
1
XX =
Specific Device Code
M
= Month Code
G
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11126D
SOT
−
563, 6 LEAD
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
ON Semiconductor and
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