onsemi-NSVUMC5NT2G
| Part # | onsemi-NSVUMC5NT2G |
Download  | onsemi-NSVUMC5NT2G |
DATA SHEET
Dual Common
Base-Collector Bias
Resistor
T
r
ansistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
SC
−
88A/SOT
−
353
CASE 419A
STYLE 6
3
2
1
R1
R2
UMC2NT1G,
NSVUMC2NT1G,
UMC3NT1G,
Q2
R2
NSVUMC3NT1G,
UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
Q1
R1
4
5
MARKING DIAGRAM
The Bias Resistor Transistor (BRT) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base
−
emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the UMC2NT1G series, two
complementary BRT devices are housed in the SOT
−
353 package
which is ideal for low power surface mount applications where board
space is at a premium.
5
4
Ux M
G
G
1
2
3
Ux
= Device Marking
= 2, 3 or 5
x
M
G
= Date Code
= Pb
−
Free Package
(Note: Microdot may be in either location)
Features
•
Simplifies Circuit Design
•
Reduces Board Space
•
Reduces Component Count
•
Available in 8 mm, 7 inch/3000 Unit Tape and Reel
•
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC
−
Q101
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information in the package
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant*
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted, common for
A
Q and
Q ,
−
minus sign for Q
(PNP) omitted)
1
2
1
Rating
Symbol
Value
50
Unit
Vdc
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
V
CBO
CEO
V
50
Vdc
I
C
100
mAdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
*For additional information on our Pb
−
Free strategy and soldering details, please
download the
onsemi
Soldering and Mounting
T
e
chniques Reference Manual,
SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
July, 2022
−
Rev. 12
UMC2NT1/D
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted, common for Q
and Q
,
−
minus sign for Q
(PNP) omitted)
A
1
2
1
Rating
Symbol
Value
Unit
THERMAL CHARACTERISTICS
Thermal Resistance
−
Junction-to-Ambient (surface mounted)
R
833
−
65 to +150
*
150
°
C/W
°
C
q
JA
Operating and Storage
T
e
mperature Range
T , T
J stg
P
mW
A
D
1. Device
mounted on a FR-4 glass epoxy printed circuit board using the minimum recommended footprint.
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
Collector-Base Cutoff Current
I
I
nAdc
nAdc
mAdc
CBO
(V =
50
V
, I
=
0
)
−
−
−
−
100
500
CB
E
Collector-Emitter Cutoff Current
(V =
50
V
, I
=
0
)
CEO
CE
B
Emitter-Base Cutoff Current
I
EBO
(V =
6.0, I
= 0 mA)
EB
C
UMC2NT1G, NSVUMC2NT1G
−
−
−
−
−
−
0.2
0.5
1.0
UMC3NT1G, NSVUMC3NT1G
UMC5NT1G/T2G, NSVUMC5NT1G/T2G
ON CHARACTERISTICS
Collector-Base Breakdown Voltage
V
V
Vdc
Vdc
(BR)CBO
(I =
10
m
A, I
= 0)
50
50
−
−
−
−
C
E
Collector-Emitter Breakdown Voltage
(I =
2.0 mA, I
= 0)
(BR)CEO
C
B
DC Current Gain
h
FE
(V =
10
V
, I
=
5
.0 mA)
CE
C
UMC2NT1G, NSVUMC2NT1G
60
35
20
100
60
35
−
−
−
UMC3NT1G, NSVUMC3NT1G
UMC5NT1G/T2G, NSVUMC5NT1G/T2G
Collector
−
Emitter Saturation Voltage
V
Vdc
Vdc
Vdc
k
W
CE(SAT)
(I =
10 mA, I
= 0.3 mA)
−
−
−
−
−
0.25
0.2
−
C
B
Output Voltage (on)
(V =
5.0
V
, V
=
2
.5
V
, R
=
1
.0 k
W
)
V
OL
CC
B
L
Output Voltage (off)
V
OH
(V =
5.0
V
, V
=
0
.5
V
, R
=
1
.0 k
W
)
4.9
CC
B
L
Input Resistor
UMC2NT1G
UMC3NT1G
R1
15.4
7.0
3.3
22
10
4.7
28.6
13
6.1
UMC5NT1G/T2G
Resistor Ratio
UMC2NT1G
R1/R2
0.8
0.8
0.38
1.0
1.0
0.47
1.2
1.2
0.56
UMC3NT1G
UMC5NT1G/T2G
2
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
Collector-Base Cutoff Current
I
I
nAdc
nAdc
mAdc
CBO
(V =
50
V
, I
=
0
)
−
−
−
−
100
500
CB
E
Collector-Emitter Cutoff Current
(V =
50
V
, I
=
0
)
CEO
CE
B
Emitter-Base Cutoff Current
I
EBO
(V =
6.0, I
= 0 mA)
EB
C
UMC2NT1G
−
−
−
−
−
−
0.2
0.5
0.1
UMC3NT1G
UMC5NT1G/T2G
ON CHARACTERISTICS
Collector-Base Breakdown Voltage
V
V
Vdc
Vdc
(BR)CBO
(I =
10
m
A, I
= 0)
50
50
−
−
−
−
C
E
Collector-Emitter Breakdown Voltage
(I =
2.0 mA, I
= 0)
(BR)CEO
C
B
DC Current Gain
h
FE
(V =
10
V
, I
=
5
.0 mA)
CE
C
UMC2NT1G
60
35
80
100
60
140
−
−
−
UMC3NT1G
UMC5NT1G/T2G
Collector
−
Emitter Saturation Voltage
V
Vdc
Vdc
Vdc
k
W
CE(SAT)
(I =
10 mA, I
= 0.3 mA)
−
−
−
−
−
0.25
0.2
−
C
B
Output Voltage (on)
(V =
5.0
V
, V
=
3
.5
V
, R
=
1
.0 k
W
)
V
OL
CC
B
L
Output Voltage (off)
V
OH
(V =
5.0
V
, V
=
0
.5
V
, R
=
1
.0 k
W
)
4.9
CC
B
L
Input Resistor
UMC2NT1G
UMC3NT1G
R1
15.4
7.0
33
22
10
47
28.6
13
61
UMC5NT1G/T2G
Resistor Ratio
UMC2NT1G
R1/R2
0.8
0.8
0.8
1.0
1.0
1.0
1.2
1.2
1.2
UMC3NT1G
UMC5NT1G/T2G
3
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
ORDERING INFORMATION
†
Device
Package
Shipping
UMC2NT1G, NSVUMC2NT1G*
SC
−
88A/SOT
−
353
(Pb
−
Free)
3,000 /
T
a
pe & Reel
UMC3NT1G, NSVUMC3NT1G*
UMC3NT2G
SC
−
88A/SOT
−
353
(Pb
−
Free)
3,000 /
T
a
pe & Reel
3,000 /
T
a
pe & Reel
3,000 /
T
a
pe & Reel
3,000 /
T
a
pe & Reel
SC
−
88A/SOT
−
353
(Pb
−
Free)
UMC5NT1G, NSVUMC5NT1G*
UMC5NT2G, NSVUMC5NT2G*
SC
−
88A/SOT
−
353
(Pb
−
Free)
SC
−
88A/SOT
−
353
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC
−
Q101 Qualified and PPAP
Capable.
DEVICE MARKING AND RESISTOR VALUES
Transistor 1
−
PNP
Transistor 2
−
NPN
R1 (K)
R2 (K)
R1 (K)
R2 (K)
Device
Marking
UMC2NT1G, NSVUMC2NT1G
UMC3NT1G, NSVUMC3NT1G
UMC3NT2G
UMC5NT1G, NSVUMC5NT1G
UMC5NT2G, NSVUMC5NT2G
U2
U3
U3
U5
U5
22
10
22
10
10
10
10
22
10
10
47
47
22
10
10
47
47
10
4.7
4.7
250
200
150
100
50
R
= 833
°
C/W
q
JA
0
-ꢀ50
0
50
100
150
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 1. Derating Curve
4
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC2NT1G, NSVUMC2NT1G PNP TRANSISTOR
1000
10
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
1
25
°
C
75
°
C
25
°
C
T ꢁ=ꢁ-25
°
C
A
-25
°
C
100
ꢀ0.1
10
0.01
1
10
I ,
COLLECTOR CURRENT (mA)
0
ꢀ20
ꢀ40
ꢀ50
100
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 2. V
CE(sat)
versus I
C
Figure 3. DC Current Gain
4
3
2
100
10
1
25
°
C
75
°
C
f = 1 MHz
l =
0 mA
T ꢁ=ꢁ-25
°
C
A
E
T =
25
°
C
A
ꢀ0.1
1
0
ꢀ0.01
V =
5 V
O
ꢀ0.001
0
1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
10
0
10
20
30
40
50
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
25
°
C
75
°
C
1
ꢀ0.1
0
10
ꢀ20
ꢀ30
ꢀ40
ꢀ50
I ,
COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage versus Output Current
5
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC2NT1G, NSVUMC2NT1G NPN TRANSISTOR
1
1000
100
10
I /I
= 10
C B
V
CE
= 10 V
T ꢁ=ꢁ-25
°
C
A
25
°
C
T ꢁ=ꢁ75
°
C
A
25
°
C
-25
°
C
0.1
75
°
C
0.01
0.001
0
20
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 7. V
CE(sat)
versus I
C
Figure 8. DC Current Gain
4
3
100
10
25
°
C
75
°
C
f = 1 MHz
I =
0 mA
E
T ꢁ=ꢁ-25
°
C
A
T =
25
°
C
A
1
0.1
2
1
0.01
0.001
V =
5 V
O
0
0
10
20
30
40
50
0
1
2
3
4
5
6
7
8
9
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 9. Output Capacitance
Figure 10. Output Current versus Input Voltage
10
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
25
°
C
75
°
C
1
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 11. Input Voltage versus Output
Current
6
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC3NT1G PNP TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
T ꢁ=ꢁ-25
°
C
A
25
°
C
ꢀ0.1
100
-25
°
C
25
°
C
75
°
C
ꢀ0.01
10
ꢀ20
I ,
COLLECTOR CURRENT (mA)
1
10
100
0
ꢀ40
50
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 12. V
CE(sat)
versus I
C
Figure 13. DC Current Gain
4
3
100
10
1
25
°
C
75
°
C
f = 1 MHz
l =
0 mA
E
T ꢁ=ꢁ-25
°
C
A
T =
25
°
C
A
2
1
0
ꢀ0.1
ꢀ0.01
V =
5 V
O
ꢀ0.001
0
10
20
30
40
50
0
1
ꢀ2
3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 14. Output Capacitance
Figure 15. Output Current versus Input
Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
25
°
C
75
°
C
1
ꢀ0.1
0
10
ꢀ20
ꢀ30
ꢀ40
ꢀ50
I ,
COLLECTOR CURRENT (mA)
C
Figure 16. Input Voltage versus Output
Current
7
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC3NT1G NPN TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
25
°
C
25
°
C
T ꢁ=ꢁ-25
°
C
A
0.1
-25
°
C
75
°
C
100
0.01
10
0.001
1
10
I ,
COLLECTOR CURRENT (mA)
100
0
20
40
50
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 17. V
CE(sat)
versus I
C
Figure 18. DC Current Gain
4
3
2
1
0
100
10
1
75
°
C
25
°
C
f = 1 MHz
I =
0 mA
T ꢁ=ꢁ-25
°
C
A
E
T =
25
°
C
A
0.1
0.01
V =
5 V
O
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 19. Output Capacitance
Figure 20. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
1
25
°
C
75
°
C
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 21. Input Voltage versus Output
Current
8
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC5NT1G PNP TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
25
°
C
100
-25
°
C
T ꢁ=ꢁ75
°
C
A
25
°
C
0.1
-25
°
C
10
1
0.01
1
10
100
1000
0
10
20
30
40
50
60
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 22. V
CE(sat)
versus I
C
Figure 23. DC Current Gain
12
100
10
f = 1 MHz
I =
0 mA
10
8
E
75
°
C
T =
25
°
C
A
6
1
0.1
V =
5 V
O
4
SERIES 1
T ꢁ=ꢁ-25
°
C
A
2
0
25
°
C
0.01
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10
12
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 24. Output Capacitance
Figure 25. Output Current versus Input Voltage
9
UMC2NT1G, NSVUMC2NT1G, UMC3NT1G, NSVUMC3NT1G, UMC5NT1G/T2G,
NSVUMC5NT1G/T2G
TYPICAL ELECTRICAL CHARACTERISTICS — UMC5NT1G NPN TRANSISTOR
10
1
1000
V
= 10 V
CE
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
25
°
C
-25
°
C
25
°
C
75
°
C
100
T ꢁ=ꢁ-25
°
C
A
0.1
0.01
10
0
20
I ,
COLLECTOR CURRENT (mA)
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 26. V
CE(sat)
versus I
C
Figure 27. DC Current Gain
1
100
10
1
25
°
C
f = 1 MHz
I =
0 mA
75
°
C
E
T ꢁ=ꢁ-25
°
C
A
0.8
T =
25
°
C
A
0.6
0.4
0.1
0.01
0.2
0
V =
5 V
O
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 28. Output Capacitance
Figure 29. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
25
°
C
75
°
C
10
1
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 30. Input Voltage versus Output Current
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC
−
88A (SC
−
70
−
5/SOT
−
353)
CASE 419A
−
02
ISSUE L
SCALE 2:1
DATE 17
JAN 2013
A
NOTES:
1. DIMENSIONING
AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING
DIMENSION: INCH.
3. 419A
−
01 OBSOLETE. NEW STANDARD
419A
−
02.
4. DIMENSIONS
A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−
B
−
S
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D
5 PL
0.2 (0.008)
—
0.004
0.004
0.004
0.010
0.012
—
0.10
0.10
0.10
0.25
0.30
N
K
N
S
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
GENERIC MARKING
DIAGRAM*
K
H
XXXM
G
SOLDER FOOTPRINT
0.50
G
0.0197
XXX =
Specific Device Code
M
= Date Code
G
= Pb
−
Free Package
(Note: Microdot may be in either location)
0.65
0.025
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
STYLE 3:
STYLE 1:
PIN 1.
BASE
STYLE 2:
STYLE 4:
STYLE 5:
PIN 1.
ANODE
2. EMITTER
3. BASE
PIN 1.
ANODE 1
2. N/C
PIN 1.
SOURCE 1
2. DRAIN
1/2
3. SOURCE
1
4. GATE
1
PIN 1.
CATHODE
2. COMMON
ANODE
3. CATHODE
2
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
3. ANODE
2
4. CATHODE
2
5. CATHODE
1
4. COLLECTOR
5. CATHODE
4. CATHODE
3
5. CATHODE
4
5. GATE
2
STYLE 9:
STYLE 6:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 7:
STYLE 8:
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
PIN 1.
ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
PIN 1.
BASE
2. EMITTER
3. BASE
PIN 1.
CATHODE
2. COLLECTOR
3. N/C
3. EMITTER
1
4. COLLECTOR
5. COLLECTOR
2/BASE 1
4. COLLECTOR
5. COLLECTOR
4. BASE
5. EMITTER
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
SC
−
88A (SC
−
70
−
5/SOT
−
353)
PAGE 1 OF 1
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