onsemi-NTB25P06T4G
| Part # | onsemi-NTB25P06T4G |
Download  | onsemi-NTB25P06T4G |
NTB25P06, NVB25P06
MOSFET
– P-Channel,
D
2
PAK
-60
V
,
–
27.5 A
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
Features
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
•
AEC Q101 Qualified
−
NVB25P06
•
These Devices are Pb
−
Free and are RoHS Compliant
−
60 V
65 m
W
@
−
10 V
−
27.5 A
Typical Applications
•
PWM Motor Controls
•
Power Supplies
•
Converters
P
−
Channel
D
•
Bridge Circuits
G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol Value
Unit
S
Drain
−
to
−
Source Voltage
V
DSS
−
60
V
MARKING DIAGRAM
& PIN ASSIGNMENT
Gate
−
to
−
Source Voltage
−
Continuous
V
“
15
“
20
V
Vpk
GS
−
Non
−
Repetitive (t
v
10 ms)
V
GSM
p
Drain
Drain Current
−
Continuous @ T
= 25
°
C
I
27.5
80
A
Apk
A
D
4
−
Single Pulse (t
v
10
m
s)
I
p
DM
NTB
25P06G
AYWW
T
o
tal Power Dissipation @ T
= 25
°
C
P
120
W
2
A
D
1
3
Operating and Storage
T
e
mperature Range
T , T
J
−
55 to
+175
°
C
stg
2
D PAK
CASE 418B
Drain
Single Pulse Drain
−
to
−
Source Avalanche
E
600
mJ
°
C/W
°
C
AS
Gate
Source
Energy
−
Starting T
= 25
°
C
J
(V =
25
V
, V
=
1
0
V
,
DD
GS
A
Y
WW
G
= Assembly Location
=
Y
e
ar
I
= 20 A, L = 3 mH, R
= 25
W
)
L(pk)
G
= Work Week
Thermal Resistance
−
Junction
−
to
−
Case
= Pb
−
Free Package
R
R
1.25
46.8
63.2
q
JC
JA
JA
q
R
q
ORDERING INFORMATION
Maximum Lead
T
e
mperature for Soldering
Purposes, (1/8
″
from case for 10 s)
T
260
L
†
Device
Package
Shipping
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
2
NTB25P06T4G
D PAK
800 /
T
a
pe & Reel
(Pb
−
Free)
2
NVB25P06T4G
D PAK
800 /
T
a
pe & Reel
1. When
surface mounted to an FR4 board using 1
″
pad size
(Pb
−
Free)
2
(Cu Area 1.127 in
).
2. When
surface mounted to an FR4 board using the minimum recommended
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specification
Brochure, BRD8011/D.
2
pad size (Cu Area 0.412 in
).
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2019
−
Rev. 4
NTB25P06/D
NTB25P06, NVB25P06
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
(V =
0
V
, I
=
−
250
m
A)
V
V
(BR)DSS
−
60
−
−
64
−
−
GS
D
mV/
°
C
m
A
(Positive
T
e
mperature Coefficient)
Zero Gate Voltage Drain Current
I
DSS
(V =
0
V
, V
=
−
60
V
, T
=
2
5
°
C)
−
−
−
−
−
10
−
100
GS
DS
J
(V =
0
V
, V
=
−
60
V
, , T
=
1
50
°
C)
GS
DS
J
Gate
−
Body Leakage Current (V
=
15
V
, V
= 0
V
)
I
−
−
100
nA
GS
DS
GSS
Gate Threshold Voltage
V
V
mV/
°
C
W
GS(th)
(V =
V
I =
−
250
m
A)
GS, D
−
2.0
−
−
2.8
6.2
−
4.0
−
DS
(Negative Threshold
T
e
mperature Coefficient)
Static Drain
−
Source On
−
State Resistance
R
DS(on)
(V =
−
10
V
, I
=
−
12.5 A)
−
−
0.065
0.070
0.075
0.082
GS
D
(V =
−
10
V
, I
=
−
25 A)
GS
D
Forward Transconductance
(V =
−
10
V
, I
=
−
12.5 A)
gFS
Mhos
pF
−
13
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
1200
345
90
1680
480
iss
(V =
−
25
V
, V
= 0 V,
DS
GS
Output Capacitance
C
oss
F = 1.0 MHz)
Reverse Transfer Capacitance
C
180
rss
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
14
72
24
118
68
320
50
−
ns
ns
ns
ns
nC
d(on)
Rise Time
t
r
(V =
−
30
V
, I
=
−
25 A,
GS
DD
D
G
V
=
−
10 V R
= 9.1
W
)
Turn
−
Off Delay Time
Fall Time
t
43
d(off)
t
f
190
33
Gate Charge
Q
T
Q
1
Q
2
(V =
−
48
V
, I
=
−
25 A,
DS
D
6.5
15
V
=
−
10 V)
GS
−
Diode Forward On
−
Voltage
V
SD
−
−
−
1.8
−
1.4
−
2.5
−
V
(I =
−
25 A, V
= 0 V)
S
GS
(I =
−
25 A, V
= 0 V, T
= 150
°
C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
70
50
20
0.2
−
−
−
−
ns
rr
(I =
−
25 A, V
= 0 V,
S
GS
t
a
dI /dt
= 100 A/
m
s)
S
t
b
Reverse Recovery Stored Charge
Q
m
C
RR
3. Indicates
Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
NTB25P06, NVB25P06
50
45
50
V
=
−
10 V
T =
25
°
C
GS
V
DS
≥
10 V
J
−
7 V
−
8 V
T =
25
°
C
J
−
9 V
40
35
40
30
20
30
25
T =
−
55
°
C
J
−
6 V
T =
125
°
C
J
−
5.5 V
−
5 V
20
15
10
5
10
0
−
4.5 V
−
4.2 V
0
0
2
4
6
8
10
2
4
6
8
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.2
0.15
0.1
0.095
0.085
V
GS
=
−
10 V
T =
25
°
C
J
T =
125
°
C
J
V
GS
=
−
10 V
T =
25
°
C
J
0.075
0.065
T =
−
55
°
C
V
GS
=
−
15 V
J
0.05
0
0
10
20
30
40
50
10
20
30
40
50
−
I ,
DRAIN CURRENT (AMPS)
D
−
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance vs. Drain Current and
Figure 4. On
−
Resistance vs. Drain Current and
Temperature
Gate Voltage
10000
1000
100
1.75
1.5
1.25
1
V
GS
= 0 V
I
V
=
−
25 A
D
=
−
10 V
GS
T =
150
°
C
J
T =
125
°
C
J
0.75
0.5
10
−
50
−
25
0
25
50
75
100 125
150
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NTB25P06, NVB25P06
3000
2500
2000
1500
1000
10
Q
V
= 0 V
V
= 0 V
T
T =
25
°
C
DS
GS
J
V
DS
C
8
6
4
2
0
iss
V
GS
Q
Q
1
2
C
rss
C
C
iss
oss
500
0
I
D
=
−
25 A
C
rss
T =
25
°
C
J
−
V
GS
−
V
DS
10
5
0
5
10
15
20
25
0
4
10
15
20
25
30
35
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE
(VOLTS)
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
1000
100
10
25
20
15
10
5
V
= 0 V
GS
T =
25
°
C
J
t
t
r
f
t
d(off)
t
d(on)
V
DD
=
−
30 V
I
D
=
−
25 A
V
=
−
10 V
GS
1
0
1
10
R ,
GATE RESISTANCE (
W
)
100
0
0.25
0.5
0.75
1
1.25
1.5
1.75
−
V ,
SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
600
V
GS
=
−
20 V
I
D
=
−
25 A
SINGLE PULSE
= 25
°
C
500
400
T
C
100
10
dc
10 ms
1 ms
100
m
s
300
200
100
0
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
25
50
75
100
125
150
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D
2
PAK 3
CASE 418B
−
04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING
AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING
DIMENSION: INCH.
3. 418B
−
01 THRU 418B
−
03 OBSOLETE,
NEW STANDARD 418B
−
04.
E
V
W
−
B
−
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.89
1.40
8.89
A
S
1
2
3
2.54 BSC
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
−
T
−
SEATING
PLANE
K
W
J
K
L
G
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625 14.60 15.88
0.045 0.055
M
N
P
R
S
V
H
D
3 PL
M
M
T B
0.13 (0.005)
1.14
1.40
VARIABLE
CONFIGURATION
ZONE
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W
−
W
VIEW W
−
W
VIEW W
−
W
1
2
3
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
STYLE 5:
PIN 1.
CATHODE
2. ANODE
STYLE 6:
PIN 1.
NO CONNECT
2. CATHODE
PIN 1.
BASE
PIN 1.
GATE
PIN 1.
ANODE
2. CATHODE
3. ANODE
PIN 1.
GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
3. CATHODE
4. ANODE
3. ANODE
4. CATHODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D
2
PAK 3
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
D
2
PAK 3
CASE 418B
−
04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
AYWW
xxxxxxxxG
AKA
xxxxxxxxG
AYWW
IC
Standard
Rectifier
xx
A
WL
Y
= Specific Device Code
= Assembly Location
= Wafer Lot
=
Y
e
ar
WW
G
AKA
= Work Week
= Pb
−
Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
3.
2
5
X
04
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D
2
PAK 3
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
onsemi
,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
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reserves the right to make changes at any time to any
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−
is” and
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onsemi
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onsemi
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:
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