onsemi-NTD20N06LT4G
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NTD20N06L, NTDV20N06L
N-Channel, Logic Level,
DPAK/IPAK
20 A, 60 V
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
20 A
(Note 1)
60 V
39 m
W@
5.0 V
Features
•
AEC Q101 Qualified
−
NTDV20N06L
•
These Devices are Pb
−
Free and are RoHS Compliant
D
Typical Applications
•
Power Supplies
•
Converters
•
Power Motor Controls
•
Bridge Circuits
N
−
Channel
G
S
4
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
4
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
1
Drain
−
to
−
Source Voltage
V
60
60
2
1
DSS
DGR
2
3
3
Drain
−
to
−
Gate Voltage (R
= 10 M
W
)
V
GS
DPAK
IPAK
CASE 369D
STYLE 2
Gate
−
to
−
Source Voltage
−
Continuous
CASE 369C
STYLE 2
V
V
15
20
GS
GS
−
Non
−
repetitive (t
v
10 ms)
p
Drain Current
MARKING DIAGRAMS
& PIN ASSIGNMENTS
−
Continuous @ T
= 25
°
C
I
I
20
10
60
Adc
Apk
A
D
D
−
Continuous @ T
= 100
°
C
A
−
Single Pulse (t
v
10
m
s)
4
4
p
I
DM
Drain
Drain
T
o
tal Power Dissipation @ T
= 25
°
C
P
60
W
W/
°
C
W
A
D
Derate above 25
°
C
0.40
1.88
1.36
A
A
W
Operating and Storage
T
e
mperature Range
T , T
−
55 to
+175
°
C
J
stg
2
1
Gate
3
Drain
Single Pulse Drain
−
to
−
Source Avalanche
E
128
mJ
AS
Source
1
2
3
Energy
−
Starting T
= 25
°
C
J
(V =
25 Vdc, V
= 5.0 Vdc,
Gate Drain Source
DD
GS
L = 1.0 mH, I
(pk) = 16 A, V
= 60 Vdc)
L
DS
A
Y
WW
20N6L
G
= Assembly Location*
Thermal Resistance
°
C/W
=
Y
e
ar
−
Junction
−
to
−
Case
R
R
2.5
80
110
= Work Week
= Device Code
= Pb
−
Free Package
q
JC
JA
JA
q
R
q
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
°
C
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
1. When
surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in
).
ORDERING INFORMATION
this data sheet.
2. When
surface mounted to an FR4 board using recommended pad size,
2
(Cu Area 0.412 in
).
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May, 2019
−
Rev. 5
NTD20N06L/D
NTD20N06L, NTDV20N06L
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
(V =
0 Vdc, I
= 250
m
Adc)
V
Vdc
(BR)DSS
60
71.3
71.2
−
−
GS
D
T
e
mperature Coefficient (Positive)
−
mV/
°
C
m
Adc
Zero Gate Voltage Drain Current
I
DSS
(V =
60 Vdc, V
= 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V =
60 Vdc, V
= 0 Vdc, T
= 150
°
C)
DS
GS
J
Gate
−
Body Leakage Current (V
=
15 Vdc, V
= 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
GSS
V
GS(th)
(V =
V ,
I =
250
m
Adc)
1.0
−
1.6
4.6
2.0
−
DS
GS
D
Threshold
T
e
mperature Coefficient (Negative)
mV/
°
C
m
W
R
V
DS(on)
(V =
5.0 Vdc, I
= 10 Adc)
−
39
48
GS
D
(V =
5.0 Vdc, I
= 20 Adc)
Vdc
DS(on)
−
−
0.81
0.72
1.66
−
GS
D
(V =
5.0 Vdc, I
= 10 Adc, T
= 150
°
C)
GS
D
J
g
FS
−
17.5
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
707
224
72
990
320
105
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
Turn
−
On Delay Time
Rise Time
C
oss
f = 1.0 MHz)
C
rss
t
−
−
−
−
−
−
−
9.6
98
20
200
50
120
32
−
ns
d(on)
(V =
30 Vdc, I
= 20 Adc,
DD
D
t
r
V
GS
= 5.0 Vdc,
Turn
−
Off Delay Time
Fall Time
t
25
d(off)
R
G
t
f
62
Q
T
Q
1
Q
2
16.6
5.5
8.5
nC
Gate Charge
(V =
48 Vdc, I
= 20 Adc,
DS
V
D
GS
−
SOURCE
−
DRAIN DIODE CHARACTERISTICS
Forward On
−
Voltage
V
SD
−
−
0.97
0.85
1.2
Vdc
ns
S
GS
(I =
20 Adc, V
= 0 Vdc, T
= 150
°
C)
−
S
GS
J
t
rr
−
−
−
−
42
30
−
−
−
−
Reverse Recovery Time
(I =
20 Adc, V
= 0 Vdc,
S
GS
t
a
S
t
b
12
Reverse Recovery Stored Charge
Q
0.066
m
C
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
Package
Shipping
NTD20N06LG
DPAK
(Pb
−
Free)
75 Units / Rail
NTD20N06L
−
1G
NTD20N06LT4G
IPAK (Straight Lead)
75 Units / Rail
(Pb
−
Free)
DPAK
(Pb
−
Free)
2500 /
T
a
pe & Reel
2500 /
T
a
pe & Reel
NTDV20N06LT4G
DPAK
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
2
NTD20N06L, NTDV20N06L
40
30
20
10
40
V
= 10 V
GS
V
≥
10 V
DS
4.5 V
4 V
8 V
5 V
30
6 V
20
10
3.5 V
3 V
T =
25
°
C
J
T =
100
°
C
J
T =
−
55
°
C
J
0
0
0
1
2
3
4
5
1.6
2.4
3.2
4
4.8
5.6
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.085
0.075
0.065
0.055
0.045
0.035
0.025
0.015
0.085
0.075
0.065
0.055
V
GS
= 5 V
V
GS
= 10 V
T =
100
°
C
J
T =
100
°
C
J
T =
25
°
C
J
0.045
0.035
0.025
0.015
T =
25
°
C
J
T =
−
55
°
C
J
T =
−
55
°
C
J
0
10
20
30
40
0
10
20
30
40
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance versus
Gate
−
to
−
Source Voltage
Figure 4. On
−
Resistance versus Drain Current
and Gate Voltage
10000
1000
2
1.8
1.6
V
GS
= 0 V
I
V
= 10 A
D
= 5 V
GS
T =
150
°
C
J
1.4
1.2
1
100
10
T =
100
°
C
J
0.8
0.6
−
50
−
25
0
25
50
75 100
125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
versus Voltage
3
NTD20N06L, NTDV20N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
a voltage corresponding to the off
−
state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on
−
state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain
−
gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
−
V )
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn
−
on and turn
−
off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
−
V )]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
2400
V
DS
= 0 V
V
GS
= 0 V
T =
25
°
C
J
2000
1600
1200
800
C
iss
C
rss
C
iss
400
0
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
NTD20N06L, NTDV20N06L
1000
6
5
4
3
2
V
I
= 30 V
= 20 A
DS
Q
D
T
V
GS
= 5 V
V
100
GS
Q
t
r
Q
2
1
t
f
t
d(off)
10
1
t
d(on)
1
0
I
= 20 A
D
T =
25
°
C
J
0
4
8
12
16
20
1
10
100
Q ,
TOTAL GATE CHARGE (nC)
G
R ,
GATE RESISTANCE (OHMS)
G
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Voltage versus Total Charge
DRAIN
−
TO
−
SOURCE DIODE CHARACTERISTICS
20
V
GS
= 0 V
T =
25
°
C
J
16
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain
−
to
−
source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non
−
linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Although many E
−
FETs can withstand the stress of
drain
−
to
−
source avalanche at currents up to rated pulsed
Switching between the off
−
state and the on
−
state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded and the
continuous current (I
), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 1
0
m
s. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I
can safely be assumed to
exceed (T
−
T )/(R
).
D
J(MAX)
C
q
JC
equal the values indicated.
A Power MOSFET designated E
−
FET can be safely used
in switching circuits with unclamped inductive loads. For
5
NTD20N06L, NTDV20N06L
SAFE OPERATING AREA
100
10
140
V
= 15 V
I
D
= 16 A
GS
SINGLE PULSE
120
100
80
10
m
s
T
C
= 25
°
C
100
m
s
1 ms
60
10 ms
1
dc
40
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
20
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
10
50% Duty Cycle
1
20%
10%
5%
0.1
2%
1%
Single Pulse
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D
−
01
ISSUE C
DATE 15 DEC 2010
C
B
NOTES:
SCALE 1:1
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
R
2. CONTROLLING
DIMENSION: INCH.
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
S
1
2
3
−
T
−
SEATING
PLANE
2.29 BSC
K
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D
3 PL
G
M
T
0.13 (0.005)
MARKING
DIAGRAMS
STYLE 1:
PIN 1.
BASE
STYLE 2:
STYLE 3:
PIN 1.
ANODE
STYLE 4:
PIN 1.
CATHODE
2. ANODE
Integrated
Circuits
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
Discrete
3. GATE
4. ANODE
xxxxx
ALYWW
x
YWW
xxxxxxxx
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
xxxxxxxxx =
Device Code
A
= Assembly Location
lL
Y
= Wafer Lot
=
Y
e
ar
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
D
E
C
A
b3
B
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
b2
0.028 0.045
b3
0.180 0.215
MILLIMETERS
L4
b2
e
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
BOTTOM VIEW
A
SIDE VIEW
b
b
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2
0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
PLANE
C
0.020 BSC
L3
0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−−
0.040
0.155
−−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 9
0
5
CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1.
BASE
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
PIN 1.
ANODE
STYLE 4:
STYLE 5:
PIN 1.
GATE
PIN 1.
CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
2. ANODE
3. CATHODE
4. ANODE
3. EMITTER
3. SOURCE
4. DRAIN
3. GATE
XXXXXXG
ALYWW
AYWW
XXX
4. COLLECTOR
4. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
STYLE 8:
PIN 1.
N/C
STYLE 9:
PIN 1.
ANODE
2. CATHODE
STYLE 10:
PIN 1.
CATHODE
2. ANODE
XXXXXG
PIN 1.
GATE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
3. ANODE
4. CATHODE
3. RESISTOR
ADJUST
4. CATHODE
3. CATHODE
4. ANODE
4. COLLECTOR
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX =
Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
=
Y
e
ar
= Work Week
= Pb
−
Free Package
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
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