onsemi-NTD24N06LT4G
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NTD24N06L, STD24N06L
Power MOSFET
24 A, 60
V
,
L
ogic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
24 AMPERES, 60 VOLTS
R
DS(on)
= 0.036
W (
Typ)
•
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
D
•
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
•
Power Supplies
•
Converters
•
Power Motor Controls
•
Bridge Circuits
N−Channel
G
S
4
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
2
1
Rating
Symbol Value
Unit
Vdc
Vdc
Vdc
3
Drain−to−Source Voltage
V
60
60
DPAK
DSS
DGR
CASE 369C
(Surface Mount)
STYLE 2
Drain−to−Gate Voltage (R
= 10 M
W
)
V
GS
Gate−to−Source Voltage
− Continuous
V
V
“
15
“
20
GS
GS
− Non−repetitive (t
v
10 ms)
p
MARKING DIAGRAM
& PIN ASSIGNMENT
Drain Current
− Continuous @ T
= 25
°
C
I
24
10
72
Adc
Apk
A
D
− Continuous @ T
= 100
°
C
I
D
A
4
− Single Pulse (t
v
10
m
s)
I
p
DM
Drain
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
62.5
0.42
1.88
1.36
W
W/
°
C
W
A
Derate above 25
°
C
A
W
A
Operating and Storage
T
e
mperature Range
T , T
−
5
5 to
+175
°
C
J
stg
2
1
Gate
3
Drain
Single Pulse Drain−to−Source Avalanche
E
AS
162
mJ
Source
Energy − Starting T
= 25
°
C
J
(V =
50 Vdc, V
= 5.0 Vdc,
DD
GS
A
Y
= Assembly Location*
=
Y
e
ar
= Work Week
= Device Code
= Pb−Free Package
L = 1.0 mH, I
(pk) = 18 A, V
= 60 Vdc)
L
DS
Thermal Resistance
− Junction−to−Case
°
C/W
°
C
WW
24N6L
G
R
R
R
2.4
80
110
q
JC
JA
JA
q
q
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
Maximum Lead
T
e
mperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When
surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When
surface mounted to an FR4 board using minimum recommended pad
size.
ORDERING INFORMATION
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 4
NTD24N06L/D
NTD24N06L, STD24N06L
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
(V =
0 Vdc, I
= 250
m
Adc)
V
Vdc
(BR)DSS
60
−
71.9
69.6
−
−
GS
D
mV/
°
C
m
Adc
T
e
mperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
DSS
GSS
−
−
−
−
1.0
10
(V =
60 Vdc, V
= 0 Vdc)
DS
GS
(V =
60 Vdc, V
= 0 Vdc, T
= 150
°
C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V
= 0 Vdc)
I
−
−
100
nAdc
Vdc
GS
DS
V
GS(th)
DS(on)
DS(on)
1.0
−
1.7
5.0
2.0
−
(V =
V ,
I =
250
m
Adc)
DS
GS
D
mV/
°
C
m
W
Threshold
T
e
mperature Coefficient (Negative)
R
V
−
−
36
36
45
−
(V =
5.0 Vdc, I
= 10 Adc)
GS
D
(V =
5.0 Vdc, I
= 12 Adc)
GS
D
(V =
5.0 Vdc, I
= 20 Adc)
Vdc
−
−
−
0.9
0.9
0.78
1.2
−
−
GS
D
(V =
5.0 Vdc, I
= 24 Adc)
GS
D
(V =
5.0 Vdc, I
= 12 Adc, T
= 150
°
C)
GS
D
J
g
FS
−
19
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
814
258
80
1140
360
115
iss
(V =
25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Transfer Capacitance
C
rss
Turn−On Delay Time
ns
t
−
−
−
−
−
−
−
9.4
97
23
52
16
3.4
11
20
200
50
100
32
−
d(on)
(V =
30 Vdc, I
= 24 Adc,
DD
D
Rise Time
t
r
V
G
= 5.0 Vdc,
GS
Turn−Off Delay Time
Fall Time
t
d(off)
R
t
f
Gate Charge
nC
Q
T
Q
1
Q
2
(V =
48 Vdc, I
= 24 Adc,
DS
D
V
GS
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
SD
−
−
−
0.93
0.95
0.86
1.1
−
−
Vdc
ns
S
GS
(I =
24 Adc, V
= 0 Vdc)
S
GS
(I =
24 Adc, V
= 0 Vdc, T
= 150
°
C)
S
GS
J
Reverse Recovery Time
t
rr
−
−
−
−
49
30
−
−
−
−
(I =
24 Adc, V
= 0 Vdc,
S
GS
t
a
S
t
b
20
Reverse Recovery Stored Charge
Q
0.084
m
C
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
NTD24N06LT4G
Package
Shipping
DPAK
2500 /
T
a
pe & Reel
(Pb−Free)
STD24N06LT4G*
DPAK
(Pb−Free)
2500 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
2
NTD24N06L, STD24N06L
50
40
30
20
10
50
5 V
V
DS
≥
10 V
V
= 10 V
GS
4.5 V
T =
25
°
C
J
40
30
20
10
8 V
6 V
4 V
3.5 V
3 V
T =
−55
°
C
J
T =
100
°
C
J
0
0
0
1
2
3
4
1.6
2.4
3.2
4
4.8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.08
0.06
0.04
0.1
0.08
0.06
0.04
V
GS
= 5 V
V
GS
= 10 V
T =
100
°
C
J
T =
100
°
C
J
T =
25
°
C
J
T =
25
°
C
J
T =
−55
°
C
J
0.02
0
0.02
0
T =
−55
°
C
J
0
10
20
30
40
50
0
10
20
30
40
50
I ,
DRAIN CURRENT (AMPS)
D
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
1000
2
1.8
1.6
V
GS
= 0 V
I
V
= 12 A
D
= 5 V
GS
T =
150
°
C
J
1.4
1.2
100
1
1
T =
100
°
C
J
0.8
0.6
−50 −25
0
25
50
75 100
125 150 175
0
10
20
30
40
50
60
T , JUNCTION TEMPERATURE (
°
C)
J
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
3
NTD24N06L, STD24N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure
9) shows how typical switching
performance is affected by the parasitic circuit elements.
If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most
power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load.
Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used.
In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore,
rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant.
The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
2800
V
DS
= 0 V
V
GS
= 0 V
T =
25
°
C
J
2400
2000
1600
1200
800
C
iss
C
rss
C
iss
C
400
0
oss
C
5
rss
10
5
0
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
NTD24N06L, STD24N06L
1000
6
5
4
3
2
Q
T
Q
Q
2
1
V
GS
100
t
r
t
f
t
d(off)
10
1
t
d(on)
V
I
= 30 V
= 24 A
DS
1
0
I
= 24 A
D
D
T =
25
°
C
J
V
GS
= 5 V
0
4
8
12
16
20
1
10
R ,
GATE RESISTANCE (OHMS)
100
Q ,
TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
24
V
GS
= 0 V
T =
25
°
C
J
20
16
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded and the
continuous current (I
), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 1
0
m
s. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I
can safely be assumed to
exceed (T
− T
)/(R ).
D
J(MAX)
C
q
JC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
5
NTD24N06L, STD24N06L
SAFE OPERATING AREA
100
10
180
V
= 15 V
I
D
= 18 A
GS
160
SINGLE PULSE
10
m
s
T
C
= 25
°
C
140
120
100
m
s
100
80
1 ms
10 ms
1
60
40
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
20
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.05
0.02
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
SINGLE PULSE
t
1
1
t
2
T
J(pk)
− T
= P
R
q
(t)
JC
C
(pk)
DUTY CYCLE, D = t
/t
1
2
0.01
1.0E-05
1.0E-04
1.0E-03
1.0E-02
t, TIME (
m
s)
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
6
NTD24N06L, STD24N06L
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
L4
Z
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
MILLIMETERS
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
BOTTOM VIEW
A
ALTERNATE
SIDE VIEW
CONSTRUCTION
b
b
b2
0.028 0.045
b3
0.180 0.215
M
0.005 (0.13)
C
H
TOP VIEW
c
0.018 0.024
GAUGE
PLANE
SEATING
PLANE
c2
0.018 0.024
L2
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L
A1
L1
0.020 BSC
DETAIL A
ROTATED 9
0
5
CW
L3
0.035 0.050
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
STYLE 2:
PIN 1.
GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at
www.onsemi.com/site/pdf/Patent−Marking.pdf
. SCILLC
reserves the right to make changes without further notice to any products herein.
SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time.
All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer.
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copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMEN
T
:
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: 800−282−9855
T
o
ll Free
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.
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o
ll Free USA/Canada
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o
ll Free USA/Canada
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NTD24N06L/D
