onsemi-NTD25P03LT4G
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NTD25P03L, STD25P03L
Power MOSFET
−25 A, −30 V, Logic Level P−Channel DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
The source−to−drain diode recovery time is comparable to a discrete
fast recovery diode.
V
R
Typ
I Max
D
(BR)DSS
DS(on)
Features
−30 V
51 m
W
@ 5.0 V
−25 A
•
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
D
•
These Devices are Pb−Free and are RoHS Compliant
P−Channel
Typical Applications
•
PWM Motor Controls
•
Power Supplies
•
Converters
G
S
2
4
•
Bridge Circuits
1
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
3
J
DPAK
Rating
Symbol
Value
Unit
CASE 369C
STYLE 2
Drain−to−Source Voltage
V
DSS
−30
V
Gate−to−Source Voltage
− Continuous
V
15
20
V
Vpk
MARKING DIAGRAM
& PIN ASSIGNMENT
GS
− Non−Repetitive (tp
≤
10 ms)
V
GSM
Drain Current
4
− Continuous @ T
= 25
°
C
− Single Pulse (t
≤
10
m
s)
I
−25
−75
A
Apk
A
D
Drain
I
p
DM
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
75
W
A
Operating and Storage
T
e
mperature Range
T , T
−55 to
+150
°
C
J
stg
Single Pulse Drain−to−Source Avalanche
E
200
mJ
°
C/W
°
C
AS
2
Energy − Starting T
= 25
°
C
1
Gate
3
J
Drain
(V =
25 Vdc, V
= 5.0 Vdc,
DD
GS
Source
Peak I
= 20 Apk, L = 1.0 mH, R
= 25
W
)
L
G
A
Y
= Assembly Location*
=
Y
e
ar
= Work Week
= Device Code
= Pb−Free Package
Thermal Resistance
− Junction−to−Case
R
R
1.65
67
120
q
JC
JA
JA
WW
25P03L
G
q
R
q
Maximum Lead
T
e
mperature for Soldering
Purposes, (1/8 in from case for 10 seconds)
T
260
L
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When
surface mounted to an FR4 board using 0.5 sq in pad size.
2. When
surface mounted to an FR4 board using the minimum recommended
pad size.
ORDERING INFORMATION
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 5
NTD25P03L/D
NTD25P03L, STD25P03L
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
(V =
0 Vdc, I
= −250
m
A)
V
V
(BR)DSS
−30
GS
D
−24
mV/
°
C
m
A
T
e
mperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
DSS
−1.0
−100
(V =
−30 Vdc, V
= 0 Vdc, T
= 25
°
C)
DS
GS
J
(V =
−30 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
Gate−Body Leakage Current
(V 15
Vdc, V
= 0 Vdc)
I
nA
GSS
−100
−2.0
=
GS
DS
Gate Threshold Voltage
V
GS(th)
V
mV/
°
C
W
−1.0
−1.6
4.0
(V =
V ,
I =
−250
m
Adc)
DS
GS
D
T
e
mperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
R
DS(on)
0.051
0.056
0.065
0.072
0.080
0.090
(V =
−5.0 Vdc, I
= −12.5 Adc)
GS
D
(V =
−5.0 Vdc, I
= −25 Adc)
GS
D
(V =
−4.0 Vdc, I
= −10 Adc)
GS
D
Forward Transconductance
(V =
−8.0 Vdc, I
= −12.5 Adc)
g
Mhos
pF
FS
13
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
900
290
105
1260
410
iss
(V =
−25 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
210
rss
Turn−On Delay Time
t
9.0
37
20
75
30
55
20
ns
d(on)
(V =
−15 Vdc, I
= −25 A,
Rise Time
t
r
DD
D
V
GS
= −5.0
V
,
Turn−Off Delay Time
Fall Time
t
15
R
= 1.3
W
)
d(off)
G
t
f
16
Gate Charge
Q
T
Q
1
Q
2
Q
3
15
nC
(V =
−24 Vdc,
3.0
9.0
7.0
DS
V
= −5.0 Vdc,
= −25 A)
GS
I
D
Diode Forward On−Voltage
(I =
−25 Adc, V
= 0 V)
V
SD
−1.0
−0.9
−1.5
V
S
GS
(I =
−25 Adc, V
= 0
V
, T
=
1
25
°
C)
S
GS
J
Reverse Recovery Time
t
35
20
ns
rr
(I =
−25 A, V
= 0 V,
dI /dt
= 100 A/
m
s)
S
S
GS
t
a
t
b
14
Reverse Recovery Stored Charge
Q
0.035
m
C
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperature.
2
NTD25P03L, STD25P03L
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
50
40
30
20
50
T =
25
°
C
T =
−40
°
C
V
= 10 V
J
J
GS
V
DS
≥
−5 V
9 V
8 V
5 V
6 V
T =
25
°
C
J
40
30
20
7 V
T =
125
°
C
J
4.5 V
4 V
3.5 V
10
0
10
0
3 V
2.5 V
0
1
2
3
4
5
1
2
3
4
5
6
−V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
−V ,
GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.3
0.25
0.2
0.01
0.075
0.05
V
= −5 V
GS
T =
25
°
C
J
V
= −5 V
GS
0.15
0.1
V
= −10 V
GS
T = 125
°
C
T = 25
°
C
0.025
0
0.05
0
T = −40
°
C
0
5
10
15 20
25 30 35 40 45 50
0
5
10 15
20 25 30 35 40
45 50
−I ,
DRAIN CURRENT (AMPS)
D
−I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10,000
1000
1.6
1.4
1.2
1
V
GS
= 0 V
I
V
= −12.5
D
= −5 V
GS
T =
150
°
C
J
T =
125
°
C
J
100
10
0.8
0.6
−50 −25
0
25
50
75
100
125 150
0
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
−V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
3
NTD25P03L, STD25P03L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
D
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(
A
V
)
rudimentary analysis of the drive circuit so that
t = Q/I
G(
A
V
)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
t =
Q x
R /(V
− V
)
GSP
r
2
G
GG
t =
Q x
R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R =
the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
C In
[V /(V
− V
)]
G iss
GG GG
GSP
d(on)
d(off)
= R
C In
(V /V
)
GG GSP
G
iss
2200
C
2000
1800
1600
1400
1200
1000
800
T =
25
°
C
iss
rss
J
C
C
iss
600
C
C
oss
400
200
0
rss
V
= 0 V
V
GS
= 0 V
5
−V
DS
DS
10
5
0
10
15
20
25
−V
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
NTD25P03L, STD25P03L
30
25
20
15
10
1000
10
Q
V
= −15 V
= −25 A
= −5.0 V
T
DD
I
D
−V
DS
V
GS
8
6
4
2
0
t
t
r
T =
25
°
C
J
100
f
−V
GS
t
d(off)
Q
Q
2
1
t
10
1
d(on)
I
= −25 A
T =
25
°
C
D
5
0
J
Q
3
0
2.5
5
7.5
10
12.5
15
1
10
R ,
GATE RESISTANCE (
W
)
100
Q ,
TOTAL GATE CHARGE (nC)
g
G
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t
is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t
is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
/t serves
as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t
, due
rr
to the storage of minority carrier charge, Q
, as shown in
RR
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t
and low Q
specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
25
V
GS
= 0 V
T =
25
°
C
J
20
15
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1
−V ,
SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
5
NTD25P03L, STD25P03L
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25
°
C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I
), the energy rating is specified at rated
DM
(I )
nor rated voltage (V
) is exceeded, and that the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t , t ) does not exceed 10
m
s. In addition the
custom. The energy rating must be derated for temperature
r
f
total power averaged over a complete switching cycle must
not exceed (T
− T
)/(R ).
energy at currents below rated continuous I
can safely be
D
J(MAX)
C
q
JC
assumed to equal the values indicated.
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
100
200
180
V
= −20 V
GS
I
D
= −20 A
SINGLE PULSE
T
C
= 25
°
C
160
140
120
100
100
m
s
10
1 ms
10 ms
dc
80
60
40
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
20
0
0.1
0.1
1
10
25
50
75
100
125
150
100
−V ,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
6
NTD25P03L, STD25P03L
TYPICAL ELECTRICAL CHARACTERISTICS
1
D = 0.5
0.2
0.1
0.05
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
0.01
t
1
READ TIME AT t
1
t
2
T
J(pk)
− T
= P
R
q
(t)
JC
SINGLE PULSE
C
(pk)
DUTY CYCLE, D = t
/t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
ORDERING INFORMATION
Device
†
Package
Shipping
NTD25P03LT4G
DPAK
(Pb−Free)
2500 /
T
a
pe & Reel
STD25P03LT4G*
DPAK
(Pb−Free)
2500 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
7
NTD25P03L, STD25P03L
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
L4
Z
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
MILLIMETERS
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
BOTTOM VIEW
A
ALTERNATE
SIDE VIEW
CONSTRUCTION
b
b
b2
0.028 0.045
b3
0.180 0.215
M
0.005 (0.13)
C
H
TOP VIEW
c
0.018 0.024
GAUGE
PLANE
SEATING
PLANE
c2
0.018 0.024
L2
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L
A1
L1
0.020 BSC
DETAIL A
ROTATED 9
0
5
CW
L3
0.035 0.050
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
STYLE 2:
PIN 1.
GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
0.244
3.00
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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at
www.onsemi.com/site/pdf/Patent−Marking.pdf
. SCILLC
reserves the right to make changes without further notice to any products herein.
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time.
All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts.
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:
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ll Free
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Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
Literature Distribution Center for ON Semiconductor
P
.
O. Box 5163, Denver, Colorado 80217 USA
Phone
: 303−675−2175 or 800−344−3860
T
o
ll Free USA/Canada
Fax
: 303−675−2176 or 800−344−3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NTD25P03L/D
