onsemi-NTD4855NT4H
| Part # | onsemi-NTD4855NT4H |
Download  | onsemi-NTD4855NT4H |
NTD4855N
Power MOSFET
25 V, 98 A, Single N
–
-Channel, DPAK/IPAK
Features
•
Trench Technology
•
Low R
DS(on)
to Minimize Conduction Losses
•
Low Capacitance to Minimize Driver Losses
•
Optimized Gate Charge to Minimize Switching Losses
•
These are Pb
–
-Free Devices
V
R
MAX
I
MAX
D
(BR)DSS
DS(ON)
4.3 m
Ω
@ 10 V
6.0 m
Ω
@ 4.5 V
25 V
98 A
Applications
•
VCORE Applications
•
DC
–
-DC Converters
•
Low Side Switching
D
MAXIMUM RATINGS
(T =
25
°
C unless otherwise stated)
J
G
Parameter
Symbol
Value
Unit
Drain
–
–
to
–
–
Source Voltage
Gate
–
–
to
–
–
Source Voltage
V
25
±
20
18
V
V
A
DSS
S
V
N
–
-CHANNEL MOSFET
GS
Continuous Drain
Current R
I
D
T
= 25
°
C
= 85
°
C
= 25
°
C
A
4
θ
JA
4
T
A
14
(Note 1)
Power Dissipation
(Note 1)
4
T
A
P
2.24
W
A
D
R
θ
JA
2
1
Continuous Drain
Current R
ID
T
A
= 25
°
C
= 85
°
C
= 25
°
C
14
1
1
2
3
3
θ
JA
2
T
A
10.9
1.35
Steady
State
3
(Note 2)
Power Dissipation
(Note 2)
CASE 369AC
3 IPAK
(Straight Lead)
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
CASE 369D
IPAK
(Straight Lead
DPAK)
T
A
P
I
W
A
D
R
θ
JA
Continuous Drain
T
C
T
C
T
C
= 25
°
C
= 85
°
C
= 25
°
C
98
76
D
Current R
(Note 1)
θ
JC
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Power Dissipation
(Note 1)
P
66.7
W
A
D
R
θ
JC
4
Pulsed Drain
Current
t =10
m
s
p
T
A
= 25
°
C
= 25
°
C
I
DM
197
45
Drain
4
4
Drain
Drain
Current Limited by Package
T
A
I
A
DmaxPkg
Operating Junction and Storage
T
e
mperature
T ,
STG
— 5 5
t o
+175
°
C
J
T
Source Current (Body Diode)
Drain to Source dV/dt
I
56
6
A
S
dV/dt
EAS
V/ns
mJ
2
Single Pulse Drain
–
–
to
–
–
Source Avalanche
Energy (T
= 25
°
C, V
= 50 V, V
= 10 V,
220
1
2
3
Drain
1
3
J
DD
GS
Gate Drain Source
Gate Source
I =
21 A
, L = 1.0 mH, R
= 25
Ω
)
1
2
3
L
pk
G
Gate Drain Source
Lead
T
e
mperature for Soldering Purposes
(1/8” from case for 10 s)
T
260
°
C
L
Y
WW
= Year
= Work Week
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
4855N =
Device Code
= Pb
–
–
Free Package
G
ORDERING INFORMATION
Se
e
d
etaile
d
o
rderin
g
a
n
d
s
hippin
g
i
nformatio
n
i
n
t
h
e
p
ackage
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010
–
– Rev. 3
NTD4855N/D
NTD4855N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
2.25
3.5
Unit
Junction
–
–
to
–
–
Case (Drain)
R
θ
°
C/W
JC
R
θ
JC
–
–
T
AB
Junction
–
–
to
–
–
T
AB (Drain)
Junction
–
–
to
–
–
Ambient – Steady State (Note 1)
Junction
–
–
to
–
–
Ambient – Steady State (Note 2)
R
θ
R
θ
67
JA
JA
111
1. Surface
–
–
mounted
on FR4 board using 1 sq
–
–
in pad, 1 oz Cu.
2. Surface
–
–
mounted
on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
–
–
to
–
–
Source Breakdown Voltage
V
V
= 0 V, I
= 250
m
A
25
V
(BR)DSS
GS
D
Drain
–
–
to
–
–
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
22
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0 V,
= 20 V
T =
25
°
C
1.0
10
DSS
GS
DS
J
V
m
A
T =
125
°
C
J
Gate
–
–
to
–
–
Source Leakage Current
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
I
V
= 0 V, V
=
±
20 V
±
100
nA
GSS
DS
GS
V
V
= V
, I
= 250
m
A
1.45
2.5
V
GS(TH)
GS
DS
D
Negative Threshold
T
e
mperature
Coefficient
V
/T
J
TBD
GS(TH)
mV/
°
C
Drain
–
–
to
–
–
Source On Resistance
R
V
= 10 V
I
I
= 30 A
= 30 A
3.5
4.6
80
4.3
6.0
DS(on)
GS
D
D
m
Ω
V
= 4.5 V
GS
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
V
= 1.5 V, I
= 15 A
S
FS
DS
D
C
2950
740
400
21.8
2.4
ISS
Output Capacitance
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
C
V
= 0 V, f = 1.0 MHz, V
= 12 V
pF
OSS
RSS
GS
DS
Q
32.7
G(TOT)
Threshold Gate Charge
Gate
–
–
to
–
–
Source Charge
Gate
–
–
to
–
–
Drain Charge
T
o
tal Gate Charge
Q
G(TH)
V
= 4.5 V, V
= 15 V, I
= 30 A
nC
nC
GS
DS
D
Q
7.9
GS
GD
Q
8.6
Q
t
V
= 10 V, V
= 15 V, I
= 30 A
44
G(TOT)
GS
DS
D
SWITCHING CHARACTERISTICS
(Note 4)
Turn
–
–
On Delay Time
Rise Time
17.75
31.48
20.28
10.74
10.01
16.52
32.02
4.35
d(ON)
t
r
V
= 4.5 V, V
= 15 V,
DS
= 15 A, R
= 3.0
Ω
GS
ns
ns
I
D
G
Turn
–
–
Off Delay Time
Fall Time
t
d(OFF)
t
f
Turn
–
–
On Delay Time
Rise Time
t
d(ON)
t
r
V
= 11.5 V, V
= 15 V,
DS
= 15 A, R
= 3.0
Ω
GS
I
D
G
Turn
–
–
Off Delay Time
Fall Time
t
d(OFF)
t
f
3. Pulse
T
e
st: pulse width
≤
300
m
s, duty cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
NTD4855N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DRAIN
–
-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.86
0.74
25.5
12.9
12.6
13.8
1.2
SD
J
V
S
= 0 V,
GS
V
I
= 30 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
RR
t
ns
nC
nH
a
V
= 0 V, dIS/dt = 100 A/
m
s,
GS
I
= 30 A
S
Discharge Time
t
b
Reverse Recovery Charge
PACKAGE PARASITIC VALUES
Source Inductance
Q
RR
L
L
L
2.49
0.0164
1.88
S
D
D
G
Drain Inductance, DPAK
Drain Inductance, IPAK
Gate Inductance
T
A
= 25
°
C
L
3.46
Gate Resistance
R
G
0.8
Ω
3. Pulse
T
e
st: pulse width
≤
300
m
s, duty cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
3
NTD4855N
TYPICAL PERFORMANCE CURVES
140
90
80
70
60
50
40
30
20
10
0
T =
25
°
C
10 V
3.8 V
3.6 V
J
130
120
110
100
90
80
70
60
50
40
30
20
10
V
≥
10 V
DS
3.4 V
3.2 V
3.0 V
2.8 V
T =
125
°
C
J
T =
25
°
C
J
T =
–
–
55
°
C
J
0
0
1
2
3
4
5
1
2
3
4
5
V
, DRAIN
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
V
, GATE
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On
–
-Region Characteristics
Figure 2. Transfer Characteristics
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0.007
0.006
T =
25
°
C
I
= 30 A
J
D
T =
25
°
C
J
V
= 4.5 V
0.005
0.004
0.003
GS
V
= 11.5 V
GS
0.002
2
4
6
8
10
30
40
50
60
70
80
90 100
110 120
V
, GATE
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
I ,
DRAIN CURRENT (AMPS)
D
GS
Figure 3. On
–
-Resistance vs. Gate
–
-to
–
-Source
Voltage
Figure 4. On
–
-Resistance vs. Drain Current and
Gate Voltage
1.8
1.6
1.4
1.2
1.0
0.8
0.6
10000
1000
100
10
V
= 0 V
GS
I
V
= 30 A
D
= 10 V
T =
150
°
C
GS
J
T =
125
°
C
J
T =
25
°
C
J
1
–
–
50
–
–
25
0
25
50
75 100
125 150 175
5
10
15
20
25
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On
–
-Resistance Variation with
Temperature
Figure 6. Drain
–
-to
–
-Source Leakage Current
vs. Drain Voltage
4
NTD4855N
TYPICAL PERFORMANCE CURVES
4000
3600
3200
2800
2400
2000
1600
1200
800
12
V
= 0 V
GS
C
T =
25
°
C
Q
T
iss
J
10
8
V
6
GS
Q
C
Q
1
oss
2
4
I
V
= 30 A
D
2
= 15 V
DD
400
C
rss
T =
25
°
C
J
0
0
0
2.5
5
7.5
10
12.5
15
17.5
20
0
4
8
12 16 20 24 28 32 36 40 44 48
Q ,
TOTAL GATE CHARGE (nC)
DRAIN
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
G
Figure 7. Capacitance Variation
Figure 8. Gate
–
-To
–
-Source and Drain
–
-To
–
-Source
Voltage vs. Total Charge
1000
30
25
20
15
10
5
V
= 15 V
= 30 A
= 11.5 V
V
= 0 V
DD
GS
GS
I
D
t
t
T =
25
°
C
J
d(off)
V
f
100
10
1
t
t
r
d(on)
0
1
10
100
0.2
0.4
0.6
0.8
1.0
R ,
GATE RESISTANCE (OHMS)
G
V
, SOURCE
–
–
TO
–
–
DRAIN VOLTAGE (VOLTS)
SD
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
240
220
200
180
160
140
120
100
80
I
= 21 A
D
10
m
s
100
m
s
1 ms
V
= 20 V
GS
10 ms
dc
SINGLE PULSE
= 25
°
C
T
C
1
60
R
LIMIT
DS(on)
40
THERMAL LIMIT
PACKAGE LIMIT
20
0.1
0
0.1
1
10
100
25
50
75
100
125
150
175
V
, DRAIN
–
–
TO
–
–
SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (
°
C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
5
NTD4855N
ORDERING INFORMATION
Device
†
Package
Shipping
NTD4855NT4G
DPAK
2500 /
T
a
pe & Reel
2500 /
T
a
pe & Reel
75 Units / Rail
(Pb
–
–
Free)
NTD4855NT4H
NTD4855N
–
–
1G
NTD4855N
–
–
35G
DPAK
(Pb
–
–
Free, Halide
–
–
Free)
IPAK
(Pb
–
–
Free)
IPAK Trimmed Lead
(3.5
0.15 mm)
(Pb
–
–
Free)
75 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
6
NTD4855N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
–
–
01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN
DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
D
A
E
c2
b3
B
4
2
L3
L4
Z
H
DETAIL A
1
3
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
A
b2
c
b
b
b2
0.030 0.045
b3
0.180 0.215
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2
0.018 0.024
GAUGE
SEATING
PLANE
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
L2
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
0.020 BSC
DETAIL A
L3
0.035 0.050
ROTATED 9
0
°
CW
L4
Z
— — —
0 . 0 4 0
0.155
–
–
–
–
–
–
— — —
3.93
1 . 0 1
–
–
–
–
–
–
STYLE 2:
PIN 1.
GATE
2. DRAIN
SOLDERING FOOTPRINT*
3. SOURCE
4. DRAIN
6.20
3.00
0.244
0.118
2.58
0.102
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb
–
–
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
7
NTD4855N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC
–
–
01
ISSUE O
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING
PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION
A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
B
R
C
V
E
INCHES
DIM MIN
MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.09
A
B
C
D
E
F
G
H
J
K
R
V
W
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
A
K
SEATING PLANE
W
2.29 BSC
F
0.87
0.46
3.40
4.57
0.89
1.01
0.58
3.60
5.46
1.27
0.25
J
G
H
D
3 PL
0.000 0.010 0.000
0.13 (0.005)
W
IPAK (STRAIGHT LEAD DPAK)
CASE 369D
–
–
01
ISSUE B
C
B
R
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
2. CONTROLLING
DIMENSION: INCH.
INCHES
DIM MIN
MAX
MILLIMETERS
4
2
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
S
1
3
–
– T
–
–
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
–
–
–
–
–
–
J
F
H
0.155
–
–
–
–
–
–
D
3 PL
STYLE 2:
PIN 1.
GATE
2. DRAIN
G
M
0.13 (0.005)
T
3. SOURCE
4. DRAIN
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
N. American Technical Support
: 800
–
–
282
–
–
9855
T
o
ll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81
–
–
3
–
–
5773
–
–
3850
Literature Distribution Center for ON Semiconductor
P
.
O. Box 5163, Denver, Colorado 80217 USA
Phone
: 303
–
–
675
–
–
2175 or 800
–
–
344
–
–
3860
T
o
ll Free USA/Canada
Fax
: 303
–
–
675
–
–
2176 or 800
–
–
344
–
–
3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NTD4855N/D
