onsemi-NTD4904N-1G
| Part # | onsemi-NTD4904N-1G |
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NTD4904N
N-Channel, DPAK/IPAK
30
V
,
7
9 A
Features
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Capacitance to Minimize Driver Losses
•
Optimized Gate Charge to Minimize Switching Losses
•
These are Pb
−
Free Devices
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
3.7 m
W
@ 10 V
5.5 m
W
@ 4.5 V
30 V
79 A
Applications
D
•
CPU Power Delivery
•
DC
−
DC Converters
N
−
Channel
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
G
Parameter
Drain
−
to
−
Source Voltage
Gate
−
to
−
Source Voltage
Continuous Drain
Symbol
Value
30
Unit
V
S
4
V
DSS
V
GS
“
20
17.8
V
4
I
D
A
T =
25
°
C
A
4
Current (R
)
q
JA
T =
100
°
C
A
12.6
2.6
Power Dissipation
T =
25
°
C
A
P
W
A
2
1
D
D
D
1
2
3
3
1
2
3
q
JA
Continuous Drain
I
D
T =
25
°
C
A
13
9.2
1.4
CASE 369AD
IPAK
(Straight Lead)
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
CASE 369D
IPAK
(Straight Lead
DPAK)
Current (R
) (Note
q
JA
T =
100
°
C
A
Steady
State
Power Dissipation
T =
25
°
C
A
P
I
W
A
q
JA
Continuous Drain
T
= 25
°
C
= 100
°
C
= 25
°
C
79
56
52
D
C
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Current (R
)
q
JC
T
C
4
Drain
Power Dissipation
T
C
P
W
4
4
Drain
Drain
q
JC
Pulsed Drain Current
t =10
m
s T
= 25
°
C
I
316
90
A
A
p
A
DM
I
DmaxPkg
Current Limited by Package
T =
25
°
C
A
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
175
°
C
J
stg
2
1
2
3
Source Current (Body Diode)
Drain to Source dV/dt
I
47
6.0
A
S
Drain
1
3
Gate Drain Source
Gate Source
dV/dt
V/ns
mJ
1
2
3
Gate Drain Source
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
68.4
A
Y
= Assembly Location
=
Y
e
ar
Energy (T
= 25
°
C, V
= 50
V
, V
=
1
0
V
,
J
DD
GS
L = 0.1 mH, I
= 37 A, R
= 25
W
)
L(pk)
G
WW
= Work Week
Lead
T
e
mperature for Soldering Purposes
T
260
°
C
L
4904N =
Device Code
G
(1/8
″
from case for 10 s)
= Pb
−
Free Package
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May, 2019
−
Rev. 2
NTD4904N/D
NTD4904N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction
−
to
−
Case (Drain)
R
2.9
4.3
57
°
C/W
q
JC
Junction
−
to
−
T
a
b (Drain)
R
q
JC
−
TAB
R
R
q
q
JA
JA
108
1. Surface
−
mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface
−
mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
30
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
15
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
m
A
T =
25
°
C
1.0
10
DSS
J
V
V
= 0
V
,
= 24 V
GS
DS
T =
125
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
“
20 V
“
100
nA
GSS
DS
GS
V
V
= V
, I
= 250
m
A
1.0
1.6
4.0
2.2
V
GS(TH)
GS
DS
D
Negative Threshold
T
e
mperature
Coefficient
V
/T
J
mV/
°
C
GS(TH)
Drain
−
to
−
Source On Resistance
R
V
= 10 V
GS
m
W
I
D
I
D
I
D
I
D
= 30 A
= 15 A
= 30 A
= 15 A
3.0
3.0
4.0
4.0
76
3.7
5.5
DS(on)
V
GS
= 4.5 V
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
gFS
V
DS
= 1.5
V
, I
=
3
0 A
S
D
pF
C
3052
976
23
iss
V
GS
= 0
V
, f =
1
.0 MHz,
Output Capacitance
C
oss
V
DS
= 15 V
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
rss
nC
Q
16.8
4.4
8.2
3.0
41
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
G(TH)
V
= 4.5
V
, V
=
1
5
V
,
DS
GS
I
D
= 30 A
Q
GS
GD
Q
Q
V
= 10
V
, V
=
1
5
V
,
nC
ns
G(TOT)
GS
DS
I
D
= 30 A
Turn
−
On Delay Time
Rise Time
t
15.3
19.8
23.4
7.5
d(on)
t
r
V
= 4.5
V
, V
=
1
5
V
,
DS
GS
I
D
= 15 A, R
= 3.0
W
G
Turn
−
Off Delay Time
Fall Time
t
d(off)
t
f
ns
Turn
−
On Delay Time
Rise Time
t
t
10.3
20
d(on)
t
r
V
I
= 10
V
, V
=
1
5
V
,
DS
GS
= 15 A, R
= 3.0
W
D
G
Turn
−
Off Delay Time
Fall Time
28.7
8.0
d(off)
t
f
3. Pulse
T
e
st: Pulse Width
≤
300
m
s, Duty Cycle
≤
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
NTD4904N
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
T =
25
°
C
J
0.84
0.7
1.1
V
= 0
V
,
GS
I
S
= 30 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
40.4
20.5
19.9
35
ns
RR
ta
V
GS
= 0
V
,
d
Is/dt= 100 A/
m
s,
I
S
= 30 A
Discharge Time
tb
Reverse Recovery Time
PACKAGE PARASITIC VALUES
Drain Inductance, DPAK
Gate Resistance
Q
nC
nH
RR
L
2.48
0.0164
1.88
4.9
S
D
D
G
L
L
L
T =
25
°
C
A
R
1.0
2.0
W
G
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Assume
terminal length of 110 mils.
3
NTD4904N
TYPICAL PERFORMANCE CURVES
130
130
T =
25
°
C
J
10 V
3.8 V to 6 V
3.6 V
3.4 V
V
DS
≥
10 V
120
110
100
90
120
110
100
90
3.2 V
3.0 V
2.8 V
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
T =
125
°
C
J
T =
25
°
C
J
2.6 V
2.4 V
T =
−
55
°
C
J
0
1
2
3
4
5
2
2.5
3
3.5
4
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.012
0.010
0.008
0.006
0.004
0.006
0.005
0.004
0.003
0.002
I
= 30 A
D
T =
25
°
C
J
T =
25
°
C
J
V
= 4.5 V
GS
V
= 10 V
GS
0.002
3
4
5
6
7
8
9
10
20
40
60
80
100
120
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
10,000
1000
100
2.2
2.0
V
GS
= 0 V
I
V
= 30 A
D
= 10 V
GS
T =
150
°
C
J
1.8
1.6
1.4
1.2
1.0
T =
125
°
C
J
T =
85
°
C
J
0.8
0.6
10
−
50
−
25
0
25
50
75 100 125 150 175
5
10
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
V
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Drain Voltage
4
NTD4904N
TYPICAL PERFORMANCE CURVES
3600
3200
2800
2400
2000
1600
1200
800
12
T =
25
°
C
GS
J
V
11
10
9
C
iss
= 0 V
Q
T
8
7
6
V
GS
Q
GD
5
4
3
2
1
0
Q
GS
C
oss
V
V
I
= 15 V
= 10 V
= 30 A
DD
GS
D
400
0
C
T =
25
°
C
rss
J
0
5
10
15
20
25
30
0
5
10
15
20
25
30
35
40 45
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
Q ,
TOTAL GATE CHARGE (nC)
G
Figure 7. Capacitance Variation
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
Voltage vs. Total Charge
30
25
20
15
10
1000
V
= 15 V
= 15 A
= 10 V
V
GS
= 0 V
DD
I
D
t
d(off)
V
GS
t
t
f
100
r
t
d(on)
T =
125
°
C
J
10
1
5
0
T =
25
°
C
J
1
10
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
R ,
GATE RESISTANCE (OHMS)
G
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
70
60
50
40
30
20
I
D
= 37 A
10
m
s
100
m
s
1 ms
V
= 10 V
GS
SINGLE PULSE
= 25
°
C
10 ms
dc
T
C
1
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
0
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
5
NTD4904N
TYPICAL PERFORMANCE CURVES
100
10
50% (DUTY CYCLE)
20%
10%
5.0%
2.0%
1.0
0.1
1.0%
SINGLE PULSE
0.01
PSi TAB-A
0.001
0.000001
0.00001
0.0001
0.001
0.01
PULSE TIME (s)
0.1
1.0
10
100
1000
Figure 13. FET Thermal Response
110
100
90
80
70
60
50
40
30
20
10
V
DS
= 1.5 V
0
0
10
20 30 40
50 60 70 80 90
100
ID (A)
Figure 14. GFS vs ID
ORDERING INFORMATION
Order Number
†
Package
Shipping
NTD4904NT4G
DPAK
2500 /
T
a
pe & Reel
75 Units / Rail
(Pb
−
Free)
NTD4904N
−
1G
NTD4904N
−
35G
IPAK
(Pb
−
Free)
IPAK Trimmed Lead
75 Units / Rail
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D
−
01
ISSUE C
DATE 15 DEC 2010
C
B
NOTES:
SCALE 1:1
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
R
2. CONTROLLING
DIMENSION: INCH.
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
S
1
2
3
−
T
−
SEATING
PLANE
2.29 BSC
K
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D
3 PL
G
M
T
0.13 (0.005)
MARKING
DIAGRAMS
STYLE 1:
PIN 1.
BASE
STYLE 2:
STYLE 3:
PIN 1.
ANODE
STYLE 4:
PIN 1.
CATHODE
2. ANODE
Integrated
Circuits
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
Discrete
3. GATE
4. ANODE
xxxxx
ALYWW
x
YWW
xxxxxxxx
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
xxxxxxxxx =
Device Code
A
= Assembly Location
lL
Y
= Wafer Lot
=
Y
e
ar
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
−
01
ISSUE B
4
2
1
DATE 03 JUN 2010
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
C
A
D
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
A
E
c2
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BOD
Y
.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
b3
B
4
2
L3
Z
H
DETAIL A
1
3
INCHES
DIM MIN
MAX
0.086 0.094
A1
0.000 0.005
0.025 0.035
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
L4
b2
A
c
b
b
b2
0.030 0.045
b3
0.180 0.215
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2
0.018 0.024
GAUGE
SEATING
PLANE
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
L2
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
0.020 BSC
DETAIL A
L3
0.035 0.050
ROTATED 9
0
5
CW
L4
Z
−−−
0.040
0.155
−−−
−−−
3.93
1.01
−−−
STYLE 1:
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
STYLE 4:
PIN 1.
CATHODE
2. ANODE
PIN 1.
BASE
PIN 1.
ANODE
2. CATHODE
3. ANODE
GENERIC
MARKING DIAGRAM*
2. COLLECTOR
3. EMITTER
4. COLLECTOR
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
4. CATHODE
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
XXXXXXG
ALYWW
YWW
XXX
3. CATHODE
4. ANODE
3. GATE
4. MT2
XXXXXG
SOLDERING FOOTPRINT*
IC
Discrete
6.20
0.244
3.00
0.118
XXXXXX =
Device Code
2.58
0.102
A
= Assembly Location
L
= Wafer Lot
Y
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
5.80
0.228
1.60
0.063
6.17
0.243
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD
ISSUE B
DATE 18
APR 2013
SCALE 1:1
L2
NOTES:
E
A
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
E3
E2
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TI
P
.
A1
4. DIMENSIONS
D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
D2
D
L
L1
MILLIMETERS
DIM MIN
MAX
2.38
0.60
1.10
0.89
1.10
6.22
−−−
A
A1
A2
b
b1
D
D2
E
E2
E3
e
2.19
0.46
0.87
0.69
0.77
5.97
4.80
6.35
4.57
4.45
T
SEATING
PLANE
b1
A1
e
2X
A2
E2
6.73
5.45
5.46
3X
b
M
0.13
T
2.28 BSC
D2
L
L1
L2
3.40
−−−
0.89
3.60
2.10
1.27
GENERIC MARKING
DIAGRAMS*
OPTIONAL
CONSTRUCTION
Integrated
Circuits
Discrete
AYWW
XXX
XXXXXG
STYLE 1:
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
STYLE 4:
PIN 1.
CATHODE
2. ANODE
XXXXXXG
ALYWW
PIN 1.
BASE
PIN 1.
ANODE
2. CATHODE
3. ANODE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
4. CATHODE
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
XXXXXX =
Device Code
A
= Assembly Location
L
= Wafer Lot
Y
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON23319D
3.5 MM IPAK, STRAIGHT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
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