onsemi-NTDV20P06LT4G-VF01
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NTD20P06L, NTDV20P06L
P-Channel, DPAK
-60
V
,
–
15.5 A
Features
•
Withstands High Energy in Avalanche and Commutation Modes
•
Low Gate Charge for Fast Switching
•
AEC Q101 Qualified
−
NTDV20P06L
•
These Devices are Pb
−
Free and are RoHS Compliant
I
D
MAX
V
R
TYP
DS(on)
(BR)DSS
−
60 V
130 m
W
@
−
5.0 V
−
15.5 A
Applications
•
Bridge Circuits
•
Power Supplies, Power Motor Controls
•
DC
−
DC Conversion
P
−
Channel
D
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
G
Parameter
Drain
−
to
−
Source Voltage
Symbol Value
Unit
V
V
DSS
−
60
$
20
$
30
−
15.5
S
Gate
−
to
−
Source
Voltage
Continuous
V
V
GS
MARKING DIAGRAMS
Non
−
Repetitive
t
p
v
10 ms
V
GSM
4
4
Drain
Continuous
Drain Current
Steady State
T
C
= 25
°
C
I
D
A
W
A
2
1
Power Dissipa-
tion
Steady State
T
C
= 25
°
C
P
D
65
3
DPAK
CASE 369C
STYLE 2
Pulsed Drain
Current
t =
10
m
s
p
I
$
50
DM
2
1
Gate
3
Drain
Operating Junction and Storage
T
e
mperature
T ,
STG
−
55 to
°
C
mJ
J
Source
T
175
4
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
304
4
Drain
Energy (V
= 25
V
, V
= 5 V, I
=
1
5 A,
DD
GS
PK
L = 2.7 mH, R
= 25
W
)
G
Lead
T
e
mperature for Soldering Purposes
(1/8” from case for 10 s)
T
260
°
C
L
1
2
3
IPAK/DPAK
CASE 369D
STYLE 2
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
2.3
80
Unit
1
2
3
Junction
−
to
−
Case (Drain)
R
°
C/W
q
JC
Gate Drain Source
R
q
JA
R
110
20P06L
Device Code
q
JA
A
Y
WW
G
= Assembly Location
=
Y
e
ar
= Work Week
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface
−
mounted on FR4 board using 1 in sq. pad size
(Cu area = 1.127 in sq. [1 oz] including traces)
= Pb
−
Free Package
2. Surface
−
mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.412 in sq.)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2019
−
Rev. 8
NTD20P06L/D
NTD20P06L, NTDV20P06L
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
−
250
m
A
−
60
−
74
−
64
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
mV/
°
C
(BR)DSS
J
Zero Gate Voltage Drain Current
I
T =
25
°
C
−
1.0
−
10
100
m
A
DSS
J
V
DS
= 0
V
,
GS
V
=
−
60 V
T =
150
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
20 V
nA
GSS
DS
GS
V
V
GS
= V
, I
=
−
250
m
A
−
1.0
−
1.5
3.1
−
2.0
V
mV/
°
C
W
GS(TH)
DS
D
Gate Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
V
/T
GS(TH) J
R
V
V
GS
=
−
5.0
V
, I
=
−
7.5 A
0.130
0.143
11
0.150
DS(on)
D
V
=
−
5.0
V
, I
=
−
15 A
D
GS
Forward Transconductance
g
V
=
−
10
V
, I
=
−
7.5 A
S
V
FS
DS
D
Drain
−
to
−
Source On
−
Voltage
T =
25
°
C
J
−
1.2
−
1.9
DS(on)
V
=
−
5.0
V
,
=
−
7.5 A
GS
I
D
T =
150
°
C
J
CHARGES AND CAPACITANCES
Input Capacitance
C
740
207
66
1190
300
120
26
pF
nC
ISS
Output Capacitance
C
V
GS
= 0
V
, f = 1
M
Hz, V
=
−
25 V
DS
OSS
RSS
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
Q
15
G(TOT)
V
=
−
5.0
V
, V
=
−
48
V
,
DS
GS
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Turn
−
On Delay Time
Rise Time
Q
Q
4.0
7.0
GS
GD
I
=
−
18 A
D
t
11
90
28
70
20
180
50
ns
d(ON)
t
r
V
GS
=
−
5.0
V
, V
=
−
30
V
,
DD
I
D
=
−
15 A, R
= 9.1
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
135
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
1.5
1.3
60
2.5
V
SD
J
V
GS
= 0
V
, I
=
−
15 A
S
T =
150
°
C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
39
a
V
GS
= 0
V
, d
/
d =
100 A/
m
s,
IS t
I
=
−
12 A
S
Discharge Time
21
b
Reverse Recovery Charge
Q
0.13
nC
RR
3. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%
4. Switching
characteristics are independent of operating junction temperatures
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
NTD20P06L, NTDV20P06L
TYPICAL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
40
40
35
V
=
−
6 V
V
=
−
10 V
=
−
9 V
GS
GS
T =
−
55
°
C
J
V
=
−
5.5 V
GS
V
GS
30
25
20
15
10
5
30
20
10
0
V
=
−
5 V
GS
V
=
−
8 V
=
−
7 V
GS
T =
25
°
C
J
T =
125
°
C
V
GS
J
V
GS
=
−
4.5 V
V
GS
=
−
4 V
=
−
3.5 V
=
−
3 V
V
GS
GS
V
VDS
w
10 V
T =
25
°
C
J
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 1. On
−
Region Characteristics
=
−
5 V
Figure 2. Transfer Characteristics
0.25
0.225
0.2
0.5
0.45
0.4
T =
25
°
C
J
V
GS
0.175
0.15
0.125
0.1
0.35
0.3
V
=
−
5 V
GS
T =
125
°
C
J
0.25
0.2
V
=
−
10 V
GS
T =
25
°
C
0.075
0.05
0.025
0
J
0.15
0.1
T =
−
55
°
C
J
0.05
0
0
3
6
9
12
15
18
21
24
0
5
10
15
20
25
30
−
I ,
DRAIN CURRENT (A)
D
−
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance versus Drain Current
Figure 4. On
−
Resistance versus Drain Current
and Temperature
and Gate Voltage
2
1.8
1.6
1.4
1.2
1
10000
1000
100
10
V
GS
= 0 V
I
V
=
−
7.5 A
D
=
−
5 V
GS
T =
150
°
C
J
T =
125
°
C
J
0.8
0.6
0.4
0.2
0
1
−
50
−
25
0
25
50
75
100
125
150
5
10 15 20 25 30 35 40 45 50 55
60
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (
°
C)
J
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
versus Voltage
3
NTD20P06L, NTDV20P06L
2400
2200
2000
1800
1600
1400
1200
1000
800
V
= 0 V
T =
25
°
C
J
V
GS
= 0 V
DS
C
iss
C
rss
C
iss
600
C
oss
400
C
200
rss
0
−
10
−
5
−
V
0
5
10
15
20
25
−
V
DS
GS
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE
VOLTAGE (V)
Figure 7. Capacitance Variation
60
7.5
6.25
5.0
I
D
=
−
15 A
T =
25
°
C
J
50
40
30
20
10
0
Q
G
V
DS
V
GS
3.75
2.5
Q
Q
GD
gs
1.25
0
0
4
8
12
16
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 8. Gate
−
to
−
Source and Drain
−
to
−
Source Voltage versus Total Charge
1000
100
10
20
V
= 0 V
GS
V
=
−
30 V
=
−
15 A
=
−
5 V
DD
T =
25
°
C
J
I
D
V
GS
15
10
5
t
R
t
F
t
d(off)
t
d(on)
0
1
1
10
R ,
GATE RESISTANCE (
W
)
100
0
0.25
0.5
0.75
1
1.25
1.5 1.75
−
V ,
SOURCE
−
TO
−
DRAIN VOLTAGE (V)
g
SD
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
4
NTD20P06L, NTDV20P06L
350
300
250
1000
100
10
I
D
=
−
15 A
V
=
−
15 V
GS
Single Pulse
= 25
°
C
T
C
100
200
1
150
10 ms
100
dc
1
R
Limit
DS(on)
50
Thermal Limit
Package Limit
0
0.1
0.1
1
10
100
25
50
75
100
125
150
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
10
D = 0.5
1
0.1
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.00001
0.01
0.000001
0.0001
0.001
0.01
0.1
1
t, TIME (s)
Figure 13. Thermal Response
ORDERING INFORMATION
Device
†
Package
Shipping
NTD20P06LG
75 Units / Rail
NTD20P06LT4G
2500 /
T
a
pe & Reel
2500 /
T
a
pe & Reel
2500 /
T
a
pe & Reel
DPAK
(Pb
−
Free)
NTDV20P06LT4G
NTDV20P06LT4G
−
VF01
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D
−
01
ISSUE C
DATE 15 DEC 2010
C
B
NOTES:
SCALE 1:1
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
V
E
R
2. CONTROLLING
DIMENSION: INCH.
INCHES
DIM MIN
MAX
MILLIMETERS
4
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
S
1
2
3
−
T
−
SEATING
PLANE
2.29 BSC
K
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D
3 PL
G
M
T
0.13 (0.005)
MARKING
DIAGRAMS
STYLE 1:
PIN 1.
BASE
STYLE 2:
STYLE 3:
PIN 1.
ANODE
STYLE 4:
PIN 1.
CATHODE
2. ANODE
Integrated
Circuits
PIN 1.
GATE
2. DRAIN
3. SOURCE
4. DRAIN
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. CATHODE
3. ANODE
4. CATHODE
Discrete
3. GATE
4. ANODE
xxxxx
ALYWW
x
YWW
xxxxxxxx
STYLE 5:
PIN 1.
GATE
2. ANODE
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
2. COLLECTOR
3. CATHODE
4. ANODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
xxxxxxxxx =
Device Code
A
= Assembly Location
lL
Y
= Wafer Lot
=
Y
e
ar
WW
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE G
2
1
DATE 31 MAY 2023
3
SCALE 1:1
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX =
Device Code
A
= Assembly Location
L
= Wafer Lot
STYLE 1:
STYLE 2:
PIN 1.
GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
Y
WW
G
=
Y
e
ar
= Work Week
= Pb
−
Free Package
PIN 1.
BASE
PIN 1.
ANODE
2. CATHODE
3. ANODE
PIN 1.
CATHODE
2. ANODE
3. GATE
PIN 1.
GATE
2. ANODE
3. CATHODE
4. ANODE
2. COLLECTOR
3. EMITTER
3. SOURCE
4. DRAIN
4. COLLECTOR
4. CATHODE
4. ANODE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 6:
PIN 1.
MT1
2. MT2
STYLE 7:
PIN 1.
GATE
STYLE 8:
PIN 1.
N/C
STYLE 9:
PIN 1.
ANODE
2. CATHODE
STYLE 10:
PIN 1.
CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR
ADJUST
4. CATHODE
3. CATHODE
4. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
onsemi
and
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
or its subsidiaries in the United States and/or other countries.
onsemi
reserves
the right to make changes without further notice to any products herein.
onsemi
makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does
onsemi
assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages.
onsemi
does not convey any license under its patent rights nor the rights of others.
©
Semiconductor Components Industries, LLC, 2018
onsemi
,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates
and/or subsidiaries in the United States and/or other countries.
onsemi
owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of
onsemi
’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
.
onsemi
reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as
−
is” and
onsemi
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onsemi
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. “Typical” parameters which may be provided in
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