onsemi-NTGD4167CT1G

Part #onsemi-NTGD4167CT1G
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onsemi-NTGD4167CT1G
NTGD4167C  
Power MOSFET  
Complementary, 30 V, +2.9/
−
2.2 A,  
TSOP
−
6 Dual  
Features  
•
Complementary N
−
Channel and P
−
Channel MOSFET  
•
Small Size (3 x 3 mm) Dual TSOP
−
6 Package  
•
Leading Edge Trench Technology for Low On Resistance  
•
Reduced Gate Charge to Improve Switching Response  
•
Independently Connected Devices to Provide Design Flexibility  
•
This is a Pb
−
Free Device  
V
R
MAX  
D
(BR)DSS  
DS(on)  
90 m
W
@ 4.5 V  
125 m
W
@ 2.5 V  
170 m
W
@
−
4.5 V  
300 m
W
@
−
2.5 V  
2.6 A  
2.2 A  
N
−
Ch  
30 V  
−
1.9 A  
−
1.0 A  
P
−
Ch  
−
30 V  
Applications  
•
DC
−
DC Conversion Circuits  
•
Load/Power Switching with Level Shift  
D1  
D2  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Drain
−
to
−
Source Voltage  
Gate
−
to
−
Source Voltage  
Symbol  
Value  
30  
Unit  
V
V
DSS  
G1  
G2  
(N
−
Ch & P
−
Ch)  
T =
 
25
°
C  
V
GS  
12  
V
N
−
Channel  
Continuous Drain  
Steady  
State  
I
D
2.6  
1.9  
A
A
S1  
S2  
T =
 
85
°
C  
A
N
−
CHANNEL MOSFET
 
P
−
CHANNEL MOSFET  
t
≤
5 s  
T =
 
25
°
C  
A
2.9  
P
−
Channel  
Continuous Drain  
Steady  
State  
T =
 
25
°
C  
T =
 
85
°
C  
A
I
−
1.9  
−
1.4  
A
A
D
MARKING  
DIAGRAM  
t
≤
5 s  
T =
 
25
°
C  
A
−
2.2  
0.9  
1
Power Dissipation
 
Steady State
 
T =
 
25
°
C  
P
W
A
A
D
TSOP
−
6  
CASE 318G  
STYLE 13  
TA M
G  
t
≤
5 s  
1.1  
G
Pulsed Drain  
Current  
N
−
Ch  
P
−
Ch  
t =
 
10
m
s  
p
I
8.6  
1
DM  
−
6.3  
TA =
 
Specific Device Code  
M
G
= Date Code  
= Pb
−
Free Package  
Operating Junction and Storage
T
e
mperature
 
T , T  
−
55 to  
°
C  
J
STG  
150  
(Note: Microdot may be in either location)  
Source Current (Body Diode)  
I
S
0.9  
A
Lead
T
e
mperature for Soldering Purposes  
(1/8
″
from case for 10 s)  
T
L
260  
°
C  
PIN CONNECTION  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
Value  
140  
Unit  
°
C/W  
°
C/W  
G1  
S2  
G2  
D1  
S1  
D2  
1
2
3
6
5
4
Junction
−
to
−
Ambient

Junction
−
to
−
Ambient – t
≤

R
q
JA  
R
110  
q
JA  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Surface
 
Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq  
[1 oz] including traces).  
(
T
o
p View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
©
Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
December, 2008
−
Rev. 1  
NTGD4167C/D  
 

NTGD4167C  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Symbol  
N/P  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
OFF CHARACTERISTICS  
Drain
−
to
−
Source Breakdown Voltage  
V
N
P
N
P
N
P
N
P
N
P
30  
I
= 250
m
A  
(BR)DSS  
D
V
= 0 V  
GS  
−
30  
I
D
=
−
250
m
A  
Drain
−
to
−
Source Breakdown Voltage  
T
e
mperature Coefficient  
V
/T  
21.4  
22.2  
mV/
°
C  
m
A  
(BR)DSS  
J
Zero Gate Voltage Drain Current  
I
1.0  
−
1.0  
10  
V
= 0
V
, V
 
=
2
4 V  
DS  
DSS  
GS  
T =
 
25
°
C  
J
V
GS  
= 0
V
, V
 
=
−
24 V  
DS  
V
GS  
= 0
V
, V
 
=
2
4 V  
DS  
T =
 
85
°
C  
J
V
GS  
= 0
V
, V
 
=
−
24 V  
−
10  
100  
100  
DS  
Gate
−
to
−
Source Leakage Current  
I
nA  
V
V
V
= 0
 
V
, V  
= 0
 
V
, V  
=
=
12 V  
12 V  
GSS  
DS  
DS  
GS  
GS  
ON CHARACTERISTICS

Gate Threshold Voltage  
V
N
P
N
0.5  
0.9  
1.5  
−
1.5  
90  
I
= 250
m
A  
GS(TH)  
D
V
GS  
= V  
DS  
−
0.5
−
1.1  
I
D
=
−
250
m
A  
Drain
−
to
−
Source On Resistance  
R
52  
67  
V
= 4.5 V , I
 
= 2.6 A  
D
DS(on)  
GS  
V
= 2.5 V , I
 
= 2.2 A  
125  
170  
300  
GS  
D
m
W  
P
130  
202  
2.6  
2.6  
V
=
−
4.5 V , I
 
=
−
1.9 A  
D
GS  
V
=
−
2.5
V
, I
 
=
−
1.0 A  
GS  
D
Forward Transconductance  
g
FS  
N
P
S
V
= 15
V
, I
 
=
2
.6 A  
DS  
D
V
=
−
15 V , I
 
=
−
1.9 A  
DS  
D
CHARGES AND CAPACITANCES  
Input Capacitance  
C
295  
48  
ISS  
Output Capacitance  
C
OSS  
C
RSS  
N
P
V
= 15 V  
DS  
Reverse Transfer Capacitance  
Input Capacitance  
27  
f = 1 MHz, V
 
= 0 V  
pF  
GS  
C
419  
51  
ISS  
OSS  
RSS  
Output Capacitance  
C
C
V
DS  
=
−
15 V  
Reverse Transfer Capacitance  
T
o
tal Gate Charge  
26  
Q
3.7  
0.6  
0.9  
0.8  
3.9  
0.6  
1.0  
1.0  
5.5  
6.0  
G(TOT)  
Threshold Gate Charge  
Gate
−
to
−
Source Gate Charge  
Gate
−
to
−
Drain “Miller” Charge  
T
o
tal Gate Charge  
Q
G(TH)  
N
P
V
= 4.5
V
, V
 
=
1
5
V
, I
 
=
2
.0 A  
GS DS
 
D  
Q
GS  
GD  
Q
nC  
ns  
Q
G(TOT)  
Threshold Gate Charge  
Gate
−
to
−
Source Gate Charge  
Gate
−
to
−
Drain “Miller” Charge  
Q
G(TH)  
V
GS  
=
−
4.5
V
, V
 
=
−
15
V
, I
 
=
−
2.0 A  
DS D  
Q
GS  
GD  
Q
SWITCHING CHARACTERISTICS

Turn
−
On Delay Time  
Rise Time  
t
7.0  
4.0  
14  
d(ON)  
t
r
N
P
V
= 4.5
V
, V
 
=
1
5
V
,  
DD  
GS  
D
I
= 1.0 A, R
 
= 6.0
W  
G
Turn
−
Off Delay Time  
Fall Time  
t
d(OFF)  
t
f
2.0  
8.0  
8.0  
22  
Turn
−
On Delay Time  
Rise Time  
t
d(ON)  
t
r
V
GS  
I
=
−
4.5
V
, V
 
=
−
15
V
,  
DD  
=
−
1.0 A, R
 
= 6.0
W  
D
G
Turn
−
Off Delay Time  
Fall Time  
t
d(OFF)  
t
f
8.0  
2. Pulse
 
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.  
2
 

NTGD4167C  
3. Switching
 
characteristics are independent of operating junction temperatures.  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Symbol  
N/P  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
SD  
N
P
0.7  
−
0.8  
8.0  
5.0  
3.0  
3.0  
12  
1.2  
I
= 0.9 A  
S
V
GS  
= 0
V
, T
 
=
2
5
°
C  
J
I
=
−
0.9 A  
−
1.2  
S
Reverse Recovery Time  
Charge Time  
t
ns  
RR  
t
t
a
V
GS  
= 0
V
,  
N
P
dI /
 
dt = 100 A/
m
s, I
 
= 0.9 A  
S
S
Discharge Time  
b
Reverse Recovery Charge  
Reverse Recovery Time  
Charge Time  
Q
nC  
ns  
RR  
RR  
t
t
t
10  
a
V
GS  
= 0
V
,  
dI /
 
dt = 100 A/
m
s, I
 
=
−
0.9 A  
S
S
Discharge Time  
2.0  
7.0  
b
Reverse Recovery Charge  
Q
nC  
RR  
3

NTGD4167C  
N
−
CHANNEL TYPICAL CHARACTERISTICS  
9.0  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0
9.0  
V
= 4.5 V  
T =
 
25
°
C  
GS  
J
V
DS  
= 5 V  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
3.5 V  
2.5 V  
2.0 V  
−
55
°
C  
25
°
C  
125
°
C  
1.5 V  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
0.75  
1
1.25  
1.5  
1.75  
2
2.25  
2.5  
V
DS  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
0.10  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.20  
0.18  
0.16  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
T =
 
25
°
C  
T =
 
25
°
C  
J
J
V
V
= 2.5 V  
= 4.5 V  
GS  
I
= 2.6 A  
D
GS  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0  
V
GS  
, GATE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On
−
Region vs. Gate
−
To
−
Source  
Figure 4. On
−
Resistance vs. Drain Current and  
Voltage  
Temperature  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
400  
350  
300  
250  
200  
150  
100  
50  
T =
 
25
°
C  
I
V
= 2.6 A  
J
D
V
GS  
= 0 V  
= 4.5 V  
GS  
C
ISS  
f = 1 MHz  
C
OSS  
C
RSS  
0
−
50
−
25  
0
25  
50  
75  
100  
125  
150  
0
5
10  
15  
20  
25  
30  
T , JUNCTION TEMPERATURE (
°
C)  
J
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Figure 5. On
−
Resistance Variation with  
Figure 6. Capacitance Variation  
Temperature  
4

NTGD4167C  
5
4
3
2
1
0
16  
14  
12  
10  
8
10  
1.0  
0.1  
Q
T
V
DS  
V
GS  
T =
 
150
°
C  
Q
J
GD  
Q
GS  
T =
 
25
°
C  
6
J
4
I
= 2.0 A  
D
T =
 
25
°
C  
V
J
2
= 15 V  
DS  
0
0
1
2
3
4
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
V
SD  
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
Figure 7. Gate
−
to
−
Source and  
Drain
−
to
−
Source Voltage versus Total Charge  
Figure 8. Diode Forward Voltage versus  
Current  
40  
30  
20  
10  
0
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
I
= 250
m
A  
D
−
50  
−
25  
0
25  
50  
75  
100  
125  
150  
0.001  
0.01  
0.1  
1
10  
100  
1000  
T , JUNCTION TEMPERATURE (
°
C)  
J
SINGLE PULSE TIME (s)  
Figure 9. Threshold Voltage  
Figure 10. Single Pulse Maximum Power  
Dissipation  
100  
V
GS  
= 12 V  
Single Pulse  
T =
 
25
°
C  
A
10  
1
100
m
s  
1 ms  
10 ms  
0.1  
R
Limit  
DS(on)  
Thermal Limit  
Package Limit  
dc  
0.01  
0.1  
1
10  
100  
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
5

NTGD4167C  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
Single Pulse  
0.001  
0.01  
0.0001  
0.01  
0.1  
1
10  
100  
1000  
t, TIME (s)  
Figure 12. FET Thermal Response  
6

NTGD4167C  
P
−
CHANNEL TYPICAL CHARACTERISTICS  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0
7.0  
V
DS  
=
−
5 V  
V
=
−
5.0 V to
−
3.5 V  
−
2.5 V  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0
GS  
−
3.0 V  
−
2.0 V  
−
1.5 V  
25
°
C  
125
°
C  
−
55
°
C  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
0.75  
1
1.25 1.5
 
1.75  
2
2.25 2.5
 
2.75  
3
−
V ,
 
GATE
−
TO
−
SOURCE VOLTAGE (V)  
GS  
−
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
Figure 14. Transfer Characteristics  
Figure 13. On
−
Region Characteristics  
0.5  
0.45  
0.4  
0.5  
0.45  
0.4  
T =
 
25
°
C  
J
T =
 
25
°
C  
J
0.35  
0.3  
0.35  
0.3  
V
GS  
=
−
2.5 V  
0.25  
0.2  
0.25  
0.2  
I
D
=
−
1.9 A  
V
GS  
=
−
4.5 V  
0.15  
0.1  
0.15  
0.1  
0.05  
0.05  
0
0
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
0
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
−
V ,
 
GATE VOLTAGE (V)  
GS  
−
I ,
 
DRAIN CURRENT (A)  
D
Figure 15. On
−
Region vs. Gate
−
To
−
Source  
Figure 16. On
−
Resistance vs. Drain Current  
Voltage  
and Temperature  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
550  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
T =
 
25
°
C  
J
I
V
=
−
1.9 A  
D
V
GS  
= 0 V  
=
−
4.5 V  
C
GS  
ISS  
f = 1 MHz  
C
OSS  
C
RSS  
0
−
50
−
25  
0
25  
50  
75  
100  
125  
150  
0
5
10  
15  
20  
25  
30  
T , JUNCTION TEMPERATURE (
°
C)  
J
−
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
Figure 17. On
−
Resistance Variation with  
Figure 18. Capacitance Variation  
Temperature  
7

NTGD4167C  
5
4
3
2
1
0
16  
14  
12  
10  
8
Q
T
−
V  
GS  
−
V  
DS  
Q
Q
GD  
GS  
6
I
D
=
−
2.0 A  
4
T =
 
25
°
C  
J
V
DS  
=
−
15 V  
2
0
0
1
2
3
4
Q ,
 
TOTAL GATE CHARGE (nC)  
G
Figure 19. Gate
−
to
−
Source and  
Drain
−
to
−
Source Voltage versus Total Charge  
10  
1.0  
0.1  
1.4  
1.3  
1.2  
1.1  
1.0  
I
=
−
250
m
A  
D
T =
 
150
°
C  
J
T =
 
25
°
C  
J
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
1.2  
−
50  
−
25  
0
25  
50  
75  
100  
125  
150  
−
V ,
 
SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
SD  
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 20. Diode Forward Voltage versus  
Current  
Figure 21. Threshold Voltage  
100  
10  
40  
30  
20  
10  
0
V
=
−
12 V  
GS  
Single Pulse  
T =
 
25
°
C  
A
100
m
s  
1
1 ms  
10 ms  
0.1  
R
Limit  
DS(on)  
Thermal Limit  
Package Limit  
dc  
0.01  
0.001  
0.01  
0.1  
1
10  
100  
1000  
0.1  
1
10  
100  
SINGLE PULSE TIME (s)  
−
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
Figure 22. Single Pulse Maximum Power  
Dissipation  
Figure 23. Maximum Rated Forward Biased  
Safe Operating Area  
8

NTGD4167C  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
Single Pulse  
0.001  
0.01  
0.0001  
0.01  
0.1  
1
10  
100  
1000  
t, TIME (s)  
Figure 24. FET Thermal Response  
ORDERING INFORMATION  
Device  
†
Package  
Shipping  
NTGD4167CT1G  
TSOP6  
(Pb
−
Free)  
3000 /
T
a
pe & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
9

NTGD4167C  
PACKAGE DIMENSIONS  
TSOP
−
6  
CASE 318G
−
02  
ISSUE T  
NOTES:  
D
1. DIMENSIONING
 
AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING
 
DIMENSION: MILLIMETER.  
3. MAXIMUM
 
LEAD THICKNESS INCLUDES LEAD  
FINISH THICKNESS. MINIMUM LEAD  
THICKNESS IS THE MINIMUM THICKNESS OF  
BASE MATERIAL.  
4. DIMENSIONS
 
A AND B DO NOT INCLUDE  
MOLD FLASH, PROTRUSIONS, OR GATE  
BURRS.  
6
5
2
4
E
H
E
1
3
b
MILLIMETERS  
INCHES  
DIM  
A
A1  
b
c
D
E
e
L
MIN  
0.90  
0.01  
0.25  
0.10  
2.90  
1.30  
0.85  
0.20  
2.50  
0
°  
NOM  
1.00  
0.06  
0.38  
0.18  
3.00  
1.50  
0.95  
0.40  
2.75  
−
MAX  
MIN  
0.035  
0.001  
0.010  
0.004  
0.114  
0.051  
0.034  
0.008  
0.099  
0
°  
NOM  
0.039  
0.002  
0.014  
0.007  
0.118  
0.059  
0.037  
0.016  
0.108  
−
MAX  
0.043  
0.004  
0.020  
0.010  
0.122  
0.067  
0.041  
0.024  
0.118  
1
0
°  
e
1.10  
0.10  
0.50  
0.26  
3.10  
1.70  
1.05  
0.60  
3.00  
1
0
°  
q
c
A
0.05 (0.002)  
L
A1  
H
E
q
STYLE 13:  
PIN 1.
 
GATE 1  
2. SOURCE
 
2  
3. GATE
 
2  
4. DRAIN
 
2  
5. SOURCE
 
1  
6. DRAIN
 
1  
SOLDERING FOOTPRINT*  
2.4  
0.094  
0.95  
0.037  
1.9  
0.075  
0.95  
0.037  
0.7  
0.028  
1.0  
0.039  
mm  
inches  
ǒ
Ǔ
SCALE 10:1  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
ON Semiconductor
and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
 
SCILLC reserves the right to make changes without further notice  
to any products herein.
 
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
 
All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
 
SCILLC does not convey any license under its patent rights  
nor the rights of others.
 
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
 
Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
 
SCILLC is an Equal  
Opportunity/Affirmative Action Employer.
 
This literature is subject to all applicable copyright laws and is not for resale in any manner.  
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NTGD4167C/D