onsemi-NTHC5513T1G
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NTHC5513
Complementary ChipFET
20
V
,
+
3.9 A
/ -3.0 A
Features
•
Complementary N
−
Channel and P
−
Channel MOSFET
•
Small Size, 40% Smaller than TSOP
−
6 Package
•
Leadless SMD Package Featuring Complementary Pair
•
ChipFET Package Provides Great Thermal Characteristics Similar to
Larger Packages
V
R
TYP
I MAX
D
(BR)DSS
DS(on)
60 m
W
@ 4.5 V
80 m
W
@ 2.5 V
N
−
Channel
3.9 A
20 V
•
Low R
in a ChipFET Package for High Efficiency Performance
130 m
W
@
−
4.5 V
200 m
W
@
−
2.5 V
DS(on)
P
−
Channel
−
20 V
−
3.0 A
•
Low Profile (< 1.10 mm) Allows Placement in Extremely Thin
Environments Such as Portable Electronics
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
S
D
2
1
Applications
•
Load Switch Applications Requiring Level Shift
•
DC
−
DC Conversion Circuits
•
Drive Small Brushless DC Motors
G
2
G
1
D
2
S
1
•
Designed for Power Management Applications in Portable, Battery
Powered Products
N
−
Channel MOSFET
P
−
Channel MOSFET
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol Value
Unit
V
ChipFET
CASE 1206A
STYLE 2
V
DSS
20
12
Gate
−
to
−
Source Voltage
V
GS
V
Continuous Drain
N
−
Ch
Steady
State
T =
25
°
C
I
D
2.9
A
A
PIN
MARKING
DIAGRAM
CONNECTIONS
T =
85
°
C
A
2.1
t
v
5
T =
25
°
C
3.9
A
8
7
6
5
1
2
3
4
D
D
D
D
S
1
2
3
4
8
7
6
5
1
1
2
2
1
P
−
Ch
Steady
State
T = 25
°
C
A
I
−
2.2
−
1.6
−
3.0
12
A
D
G
S
1
T = 85
°
C
A
2
t
v
5
N
−
Ch
P
−
Ch
T =
25
°
C
A
G
Pulsed Drain Current
I
A
t = 10
m
s
t = 10
m
s
2
DM
−
9.0
1.1
C1 = Specific Device Code
M =
Month Code
Power Dissipation
Steady
State
P
W
D
T =
25
°
C
A
G
= Pb
−
Free Package
t
v
5
T =
25
°
C
A
2.1
Operating Junction and Storage
T
e
mperature
T ,
STG
−
55 to
°
C
°
C
J
ORDERING INFORMATION
T
150
†
Device
NTHC5513T1G
Package
Shipping
Lead
T
e
mperature for Soldering Purposes
(1/8” from case for 10 seconds)
T
L
260
ChipFET
3000/
T
a
pe & Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface
Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
(Pb
−
Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
May, 2019
−
Rev. 5
NTHC5513/D
NTHC5513
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
110
60
Unit
Steady State
R
°
C/W
q
JA
T =
25
°
C
A
t
v
5
2. Surface
Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
V
Drain
−
to
−
Source Breakdown Voltage
V
N
P
N
P
N
P
20
I
= 250
m
A
(BR)DSS
D
V
= 0 V
GS
I
D
=
−
250
m
A
−
20
Zero Gate Voltage Drain Current
I
V
= 0
V
, V
=
1
6 V
1.0
−
1.0
5
m
A
DSS
GS
DS
V
= 0
V
, V
=
−
16 V
DS
GS
V
= 0
V
, V
=
1
6
V
, T
=
8
5
°
C
DS J
GS
V
= 0
V
, V
=
−
16
V
, T
=
8
5
°
C
−
5
GS
DS
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
12 V
100
nA
V
GSS
DS
GS
V
R
N
P
N
P
N
P
N
P
0.6
1.2
I
D
= 250
m
A
GS(TH)
V
GS
= V
DS
I
D
=
−
250
m
A
−
0.6
−
1.2
Drain
−
to
−
Source On Resistance
(on)
V
= 4.5 V , I
= 2.9 A
0.058 0.080
0.130 0.155
0.077 0.115
0.200 0.240
6.0
DS
GS
D
V
GS
=
−
4.5 V , I
=
−
2.2 A
D
W
V
= 2.5 V , I
= 2.3 A
D
GS
V
GS
=
−
2.5
V
, I
=
−
1.7 A
D
Forward Transconductance
g
V
= 10
V
, I
=
2
.9A
S
FS
DS
D
V
DS
=
−
10 V , I
=
−
2.2 A
6.0
D
CHARGES AND CAPACITANCES
Input Capacitance
C
N
P
N
P
N
P
N
P
N
P
N
P
V
= 10 V
=
−
10 V
= 10 V
180
185
80
pF
ISS
DS
V
V
V
DS
Output Capacitance
C
V
DS
DS
OSS
f = 1 MHz, V
= 0 V
GS
=
−
10 V
= 10 V
95
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
V
DS
DS
25
RSS
=
−
10 V
30
Q
V
GS
= 4.5
V
, V
=
1
0
V
, I
=
2
.9 A
2.6
3.0
0.6
0.5
0.7
0.9
4.0
6.0
nC
G(TOT)
DS
D
V
V
V
=
−
4.5
V
, V
=
−
10
V
, I
=
−
2.2 A
DS D
GS
Gate
−
to
−
Source Gate Charge
Gate
−
to
−
Drain “Miller” Charge
Q
Q
V
= 4.5
V
, V
=
1
0
V
, I
=
2
.9 A
GS DS
D
GS
GD
=
−
4.5
V
, V
=
−
10
V
, I
=
−
2.2 A
GS
DS
D
V
GS
= 4.5
V
, V
=
1
0
V
, I
=
2
.9 A
DS D
=
−
4.5
V
, V
=
−
10
V
, I
=
−
2.2 A
GS
DS
D
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: Pulse Width
v
250
m
s, Duty Cycle
v
2%.
2
NTHC5513
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Turn
−
On Delay Time
Rise Time
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
t
5.0
9.0
10
10
18
20
6.0
12
25
50
40
ns
d(ON)
t
r
N
V
= 16
V
, V
=
4
.5
V
, I
=
2
.9 A,
GS D
DD
R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
3.0
7.0
13
Turn
−
On Delay Time
Rise Time
t
d(ON)
t
r
V
=
−
16
V
, V
=
−
4.5
V
, I
=
−
2.2 A,
GS D
DD
P
R
= 2.5
W
G
Turn
−
Off Delay Time
Fall Time
t
33
d(OFF)
t
f
27
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Charge Time
V
N
P
N
P
N
P
N
P
N
P
I
= 2.6 A
0.8
1.15
V
SD
RR
S
V
= 0 V
GS
I
I
I
I
I
=
−
2.1 A
= 1.5 A
=
−
1.5 A
= 1.5 A
=
−
1.5 A
= 1.5 A
=
−
1.5 A
= 1.5 A
=
−
1.5 A
−
0.8
−
1.15
S
t
I
S
12.5
32
ns
S
t
t
I
S
9.0
10
a
S
V
GS
= 0
V
,
dI /
dt = 100 A/
m
s
S
Discharge Time
I
S
3.5
22
b
S
Reverse Recovery Charge
Q
I
S
6.0
15
nC
RR
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Switching
characteristics are independent of operating junction temperatures.
5. Pulse
T
e
st: Pulse Width
v
250
m
s, Duty Cycle
v
2%.
3
NTHC5513
TYPICAL N
−
CHANNEL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
8
6
4
8
V
= 5 V to 3 V
= 2.4 V
GS
T =
25
°
C
J
V
DS
≥
10 V
V
GS
2 V
2.2 V
6
1.8 V
4
2
0
1.6 V
1.4 V
2
0
T
C
=
−
55
°
C
25
°
C
100
°
C
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.1
0.15
0.1
I
= 2.7 A
T =
25
°
C
J
D
T =
25
°
C
J
V
= 2.5 V
= 4.5 V
GS
0.07
0.04
V
GS
0.05
0
1
3
5
7
0
1
2
3
4
5
6
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
I
D,
DRAIN CURRENT (AMPS)
Figure 4. On
−
Resistance vs. Drain Current and
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Gate Voltage
Voltage
1.7
100
10
1
I
V
= 2.7 A
V
GS
= 0 V
D
= 4.5 V
GS
1.5
1.3
1.1
T =
100
°
C
J
0.9
0.7
−
50
−
25
0
25
50
75
100
125 150
2
4
6
8
10
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
12
14
16
18
20
T , JUNCTION TEMPERATURE (
°
C)
V
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
4
NTHC5513
TYPICAL N
−
CHANNEL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
5
20
16
12
8
400
300
200
V
= 0 V
V
= 0 V
Q
DS
GS
G
T =
25
°
C
J
C
C
4.5
4
ISS
3.5
3
RSS
2.5
2
Q
1
GD
Q
GS
1.5
1
100
0
4
C
I
= 2.7 A
OSS
D
T =
25
°
C
0.5
0
J
0
3
0
0.5
1.5
2
2.5
10
5
0
5
10
15
20
V
GS
V
DS
Q ,
TOTAL GATE CHARGE (nC)
G
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
7
6
5
4
3
2
V =
0 V
GS
T =
25
°
C
J
V
= 16 V
= 2.7 A
= 4.5 V
DD
I
D
V
GS
t
r
10
t
d(OFF
)
t
d(ON)
t
f
1
0
1
1
10
R ,
GATE RESISTANCE (OHMS)
100
0.3
0.6
0.75
0.9
1.05
1.2
0.45
V
, SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
5
NTHC5513
TYPICAL P
−
CHANNEL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
4
3
2
4
T =
25
°
C
J
V
=
−
6 V to
−
3 V
=
−
2.4 V
GS
V
DS
≥
−
10 V
−
2 V
V
GS
−
2.2 V
3
−
1.8 V
−
1.6 V
2
1
0
T
=
−
55
°
C
C
1
0
−
1.4 V
−
1.2 V
25
°
C
100
°
C
0
1
2
3
4
5
6
7
8
0.5
1
1.5
2
2.5
3
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
GS
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
Figure 11. On
−
Region Characteristics
Figure 12. Transfer Characteristics
0.25
0.225
0.2
0.5
T =
25
°
C
J
I
=
−
2.1 A
D
T =
25
°
C
J
0.4
0.3
0.2
V
=
−
2.5 V
GS
0.175
0.15
0.125
0.1
V
GS
=
−
4.5 V
0.1
0
1
2
3
4
5
6
0.5
1.5
2.5
3.5
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
GS
−
I DRAIN
CURRENT (AMPS)
D,
Figure 14. On
−
Resistance vs. Drain Current
Figure 13. On
−
Resistance vs. Gate
−
to
−
Source
and Gate Voltage
Voltage
1.6
1.4
1.2
1
10000
I
V
=
−
2.1 A
V
GS
= 0 V
D
=
−
4.5 V
GS
T =
150
°
C
J
1000
100
10
T =
100
°
C
J
0.8
0.6
−
50
−
25
0
25
50
75
100
125 150
2
4
6
8
10
12
14
16
18
20
−
T , JUNCTION TEMPERATURE (
°
C)
J
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
Figure 15. On
−
Resistance Variation with
Figure 16. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
6
NTHC5513
TYPICAL P
−
CHANNEL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
5
15
12
9
600
500
400
300
200
V
DS
= 0 V
V
GS
= 0 V
T =
25
°
C
J
Q
T
C
C
−
V
ISS
−
V
GS
DS
4
3
RSS
Q
GS
Q
GD
2
1
0
6
3
I
=
−
2.1 A
T =
25
°
C
C
D
100
0
OSS
J
0
10
5
0
5
10
15
20
0
1
2
3
4
−
V
GS
−
V
DS
Q ,
TOTAL GATE CHARGE (nC)
G
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 18. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
Figure 17. Capacitance Variation
1000
2.5
2
V
GS
= 0 V
T =
25
°
C
J
100
1.5
1
t
d(OFF)
t
f
t
10
r
t
d(ON)
V
=
−
16 V
=
−
2.1 A
=
−
4.5 V
DD
0.5
0
I
D
V
GS
1
1
10
R ,
GATE RESISTANCE (OHMS)
100
0.3
0.5
0.7
0.9
−
V ,
SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
SD
G
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
Figure 20. Diode Forward Voltage vs. Current
TYPICAL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
2
1
Duty Cycle = 0.5
Notes:
P
DM
0.2
t
1
0.1
t
2
1
2
0.1
t
0.05
0.02
1. Duty Cycle, D =
t
2. Per Unit Base = R
= 90
°
C/W
thJA
(t)
3. T
T =
P
A
Z
q
JM
−
DM JA
Single Pulse
4. Surface Mounted
0.01
−
4
−
3
−
2
10
−
1
10
10
10
1
10
100
600
Square Wave Pulse Duration (sec)
Figure 21. Thermal Response
7
NTHC5513
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
1.092
0.043
0.635
0.025
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.254
0.010
0.66
0.66
0.026
0.026
Figure 23. Style 2
Figure 22. Basic
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead
−
frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
ChipFET is a trademark of Vishay Siliconix.
8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ChipFET
t
CASE1206A
−
03
ISSUE K
8
DATE 19
MAY 2009
1
SCALE 1:1
NOTES:
D
q
1. DIMENSIONING
AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. MOLD
GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME
TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS
A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO
MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
L
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
H
E
E
MILLIMETERS
INCHES
NOM
0.041
0.012
0.006
DIM
A
b
c
D
E
e
e1
L
MIN
1.00
0.25
0.10
2.95
1.55
NOM
1.05
MAX
MIN
MAX
0.043
0.014
0.008
0.122
0.067
e1
b
1.10
0.35
0.20
3.10
1.70
0.039
0.010
0.004
0.116
0.061
c
0.30
e
0.15
3.05
0.120
0.065
RESET
1.65
0.65 BSC
0.55 BSC
0.35
1.90
5
°
NOM
0.025 BSC
0.022 BSC
0.014
0.075
5
°
NOM
A
0.28
1.80
0.42
2.00
0.011
0.071
0.017
0.079
H
E
q
0.05 (0.002)
STYLE 1:
STYLE 2:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 3:
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1.
ANODE
2. DRAIN
PIN 1.
DRAIN
2. DRAIN
3. DRAIN
4. GATE
PIN 1.
ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1.
COLLECTOR
2. COLLECTOR
3. COLLECTOR
4. BASE
PIN 1.
ANODE
2. ANODE
3. DRAIN
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. DRAIN
2
7. DRAIN
1
8. DRAIN
1
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. CATHODE
/ DRAIN
4. DRAIN
5. SOURCE
6. GATE
7. CATHODE
8. CATHODE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
5. EMITTER
6. COLLECTOR
7. COLLECTOR
8. COLLECTOR
SOLDERING FOOTPRINT
GENERIC
MARKING DIAGRAM*
2.032
0.08
1
xxx M
G
G
xxx
M
= Specific Device Code
= Month Code
G
= Pb
−
Free Package
(Note: Microdot may be in either location)
2.362
0.093
0.65
0.025
PITCH
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
8X
0.66
0.026
0.457
0.018
8X
mm
inches
ǒ
Ǔ
Basic Style
OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03078D
ChipFET
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
ChipFET
t
CASE 1206A
−
03
ISSUE K
DATE 19 MAY 2009
ADDITIONAL SOLDERING FOOTPRINTS*
2.032
0.08
2.032
0.08
1
1
0.457
0.018
4X
2X
1.092
0.043
1.727
0.068
2.362
0.093
2.362
0.093
0.65
0.025
PITCH
4X
0.66
0.026
2X
2X
1.118
0.044
0.457
0.018
0.66
0.026
2X
mm
inches
ǒ
Ǔ
mm
inches
ǒ
Ǔ
Styles 1 and 4
Style 2
2.032
0.08
2.032
0.08
2X
2X
0.66
0.66
0.026
0.026
1
1
1.092
0.043
1.092
0.043
2.362
0.093
2.362
0.093
0.65
0.025
PITCH
0.65
0.025
PITCH
1.118
0.044
1.118
0.044
2X
0.457
0.018
2X
0.457
0.018
mm
inches
mm
inches
ǒ
Ǔ
ǒ
Ǔ
Style 3
Style 5
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03078D
ChipFET
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
onsemi
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’s product/patent coverage may be accessed at
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Marking.pdf
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