onsemi-NTHS5441T1

Part #onsemi-NTHS5441T1
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onsemi-NTHS5441T1
NTHS5441  

MOSFET

– Powe
r
,  
P-Channel, ChipFET  
-20
V
,
–
5.3 A  
Features  
•
Low R  
DS(on)  
•
Higher Efficiency Extending Battery Life  
•
Logic Level Gate Drive  
V
R
TYP  
I MAX  
D
(BR)DSS  
DS(on)  
−
20 V  
46 m
W
@
−
4.5 V  
−
5.3 A  
•
Miniature ChipFET Surface Mount Package  
•
Pb
−
Free Package is Available  
S
Applications  
G
•
Power Management in Portable and Battery
−
Powered Products; i.e.,  
Cellular and Cordless Telephones and PCMCIA Cards  
D
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
A
Steady  
State  
P
−
Channel MOSFET  
Rating  
Drain
−
Source Voltage  
Gate
−
Source Voltage  
Continuous Drain Current  
Symbol  
5 sec  
Unit  
V
V
DS  
V
GS  
−
20  
“
12  
V
8
ChipFET  
CASE 1206A  
STYLE 1  
I
D
A
(T =
 
150
°

J
1
−
5.3  
−
3.8  
−
3.9  
−
2.8  
T =
 
25
°
C  
A
T =
 
85
°
C  
A
PIN  
CONNECTIONS  
MARKING  
DIAGRAM  
Pulsed Drain Current  
I
“
20  
A
A
DM  
Continuous Source Current  
I
S
−
5.3  
−
3.9  
8
7
6
5
1
2
3
4
D
D
D
S
D
D
D
G
1
2
3
4
8
7
6
5
Maximum Power Dissipation  
P
W
D
2.5  
1.3  
1.3  
0.7  
T =
 
25
°
C  
A
T =
 
85
°
C  
A
Operating Junction and Storage  
T
e
mperature Range  
T , T  
J
−
55 to +150  
°
C  
stg  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
A3 = Specific Device Code  
M =
 
Month Code  
G
= Pb
−
Free Package  
(Note: Microdot may be in either location)  
1. Surface
 
Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq  
[1 oz] including traces).  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
NTHS5441T1  
ChipFET  
3000/
T
a
pe & Reel  
ChipFET  
(Pb
−
Free)  
NTHS5441T1G  
3000/
T
a
pe & Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our
T
a
pe and Reel Packaging Specifications  
Brochure, BRD8011/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
May, 2019
−
Rev. 13  
NTHS5441T1/D  
 

NTHS5441  
THERMAL CHARACTERISTICS  
Characteristic  
Symbol  
Typ  
Max  
Unit  
Maximum Junction
−
to
−

t
v
5 sec  
Steady State  
R
°
C/W  
q
JA  
40  
80  
50  
95  
Maximum Junction
−
to
−
Foot (Drain)  
Steady State  
R
15  
20  
°
C/W  
q
JF  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Characteristic  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Static  
Gate Threshold Voltage  
Gate
−
Body Leakage  
V
V
= V
 
, I
 
=
−
250
m
A  
−
0.6  
−
1.2  
V
GS(th)  
DS  
GS  
D
I
V
= 0
V
, V
 
=
“
12 V  
“
100  
−
1.0  
nA  
m
A  
GSS  
DS  
GS  
Zero Gate Voltage Drain Current  
I
V
=
−
16
V
, V
 
= 0 V  
GS  
DSS  
DS  
DS  
V
=
−
16
V
, V
 
= 0 V,  
−
5.0  
GS  
T =
 
85
°
C  
J
I
V
DS  
v
−
5.0
V
, V
 
=
−
4.5 V  
−
20  
A
D(on)  
GS  
Drain
−
Source On
−

r
V
GS  
V
GS  
=
−
3.6
V
, I
 
=
−
3.7 A  
−
−
0.050  
0.046  
0.06  
−
W
DS(on)  
D
=
−
4.5
V
, I
 
=
−
3.9 A  
D
V
=
−
2.5
V
, I
 
=
−
3.1 A  
0.070  
12  
0.083  
GS  
D
Diode Forward Vo

g
V
=
−
10
V
, I
 
=
−
3.9 A  
mhos  
V
fs  
DS  
D
V
SD  
I
S
=
−
2.1 A, V
 
= 0 V  
−
0.8  
−
1.2  
GS  
T
o
tal Gate Charge  
Q
9.7  
1.2  
3.6  
710  
400  
140  
14  
22  
nC  
pF  
ns  
G
V
=
−
10
V
, V
 
=
−
4.5
V
,  
GS  
DS  
Gate
−
Source Charge  
Gate
−
Drain Charge  
Input Capacitance  
Q
GS  
Q
GD  
I
=
−
3.9 A  
D
C
iss  
V
DS  
=
−
5.0 Vdc, V
 
= 0 Vdc,  
GS  
Output Capacitance  
Reverse Transfer Capacitance  
Turn
−
On Delay Time  
Rise Time  
C
oss  
f = 1.0 MHz  
C
rss  
t
30  
55  
d(on)  
V
=
−
10
V
, R
 
=
1
0
W  
L
t
r
22  
DD  
I
D
^
−
1.0 A, V  
=
−
4.5
V
,  
GEN  
Turn
−
Off Delay Time  
Fall Time  
t
42  
100  
70  
R
= 6
W  
d(off)  
G
t
f
35  
Source
−
Drain Reverse Recovery Time  
t
rr  
I =
 
−
1.1 A, di/dt = 100 A/
m
s  
F
30  
60  
2. Surface
 
Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).  
3. Pulse
 
T
e
st: Pulse Width
v
300
m
s, Duty Cycle
v
2%.  
4. Guaranteed
 
by design, not subject to production testing.  
2
 

NTHS5441  
TYPICAL ELECTRICAL CHARACTERISTICS  
20  
16  
12  
8
20  
−
5 V  
−
3.5 V  
−
3 V  
T =
 
−
55
°
C  
J
T =
 
25
°
C  
J
16  
12  
8
−
4.5 V  
−
4 V  
25
°
C  
125
°
C  
−
2.5 V  
−
2 V  
4
0
4
0
V
GS  
=
−
1.5 V  
0
0.5  
1
1.5  
2
2.5  
3
0
0.5  
1
1.5  
2
2.5  
3
−
V ,
 
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)  
GS  
−
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)  
DS  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
0.2  
0.2  
0.15  
0.1  
T =
 
25
°
C  
J
I
=
−
3.9 A  
D
T =
 
25
°
C  
J
0.15  
0.1  
V
GS  
= 2.5 V  
V
= 3.6 V  
= 4.5 V  
GS  
0.05  
0
0.05  
0
V
GS  
2
6
10  
14  
18  
20  
0
1
2
3
4
5
−
V ,
 
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)  
GS  
−
I DRAIN
 
CURRENT (AMPS)  
D,  
Figure 4. On
−
Resistance versus Drain Current  
Figure 3. On
−
Resistance versus  
Gate
−
to
−
Source Voltage  
and Gate Voltage  
1.6  
I
D
=
−
3.9 A  
V
GS  
=
−
4.5 V  
1.4  
1.2  
1
0.8  
0.6  
−
50
−
25  
0
25  
50  
75  
100  
125 150  
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 5. On
−
Resistance Variation with  
Temperature  
3

NTHS5441  
TYPICAL ELECTRICAL CHARACTERISTICS  
5
11  
10  
9
1500  
1200  
900  
Q
G
T =
 
25
°
C  
GS  
J
V
4
3
2
1
0
= 0  
8
7
6
C
C
iss  
Q
GS  
5
Q
GD  
600  
4
oss  
3
I
=
−
3.9 A  
D
T =
 
25
°
C  
Q
J
300  
0
2
C
/Q =
 
3.0  
GD GS  
rss  
1
0
0
1
2
3
4
5
6
7
8
9
10  
0
1
4
8
12  
16  
20  
−
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE ()  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
DS  
Figure 6. Capacitance Variation  
Figure 7. Gate
−
to
−
Source and  
Drain
−
to
−
Source Voltage versus Total Charge  
Duty Cycle = 0.5  
0.2  
0.1  
P
DM  
0.1  
0.05  
0.02  
PER UNIT BASE = R
 
= 80
°
C/W  
q
JA  
T
– T
 
= P
 
Z  
q
DM JA  
(t)  
JM  
A
t
1
SURFACE MOUNTED  
t
2
DUTY CYCLE, D = t
 
/t  
1
2
Single Pulse  
0.001  
0.01  
0.0001  
0.01  
0.1  
1
10  
100  
1000  
SQUARE WAVE PULSE DURATION (sec)  
Figure 8. Normalized Thermal Transient Impedance, Junction
−
to
−
Ambient  
5
4
3
2
V
= 0 V  
GS  
T =
 
25
°
C  
J
1
0
0.1  
0.3  
0.5  
0.7  
0.9  
−
V ,
 
SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)  
SD  
Figure 9. Diode Forward Voltage versus  
Current  
ChipFET is a trademark of Vishay Siliconix.  
4

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
ChipFET
t
 
CASE1206A
−
03  
ISSUE K  
8
DATE 19
 
MAY 2009  
1
SCALE 1:1  
NOTES:  
D
q
1. DIMENSIONING
 
AND TOLERANCING PER ANSI Y14.5M, 1982.  
2. CONTROLLING
 
DIMENSION: MILLIMETER.  
3. MOLD
 
GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.  
4. LEADFRAME
 
TO MOLDED BODY OFFSET IN HORIZONTAL  
AND VERTICAL SHALL NOT EXCEED 0.08 MM.  
5. DIMENSIONS
 
A AND B EXCLUSIVE OF MOLD GATE BURRS.  
6. NO
 
MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD  
SURFACE.  
L
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
H
E
E
MILLIMETERS  
INCHES  
NOM  
0.041  
0.012  
0.006  
DIM  
A
b
c
D
E
e
e1  
L
MIN  
1.00  
0.25  
0.10  
2.95  
1.55  
NOM  
1.05  
MAX  
MIN  
MAX  
0.043  
0.014  
0.008  
0.122  
0.067  
e1  
b
1.10  
0.35  
0.20  
3.10  
1.70  
0.039  
0.010  
0.004  
0.116  
0.061  
c
0.30  
e
0.15  
3.05  
0.120  
0.065  
RESET  
1.65  
0.65 BSC  
0.55 BSC  
0.35  
1.90  
5
°
NOM  
0.025 BSC  
0.022 BSC  
0.014  
0.075  
5
°
NOM  
A
0.28  
1.80  
0.42  
2.00  
0.011  
0.071  
0.017  
0.079  
H
E
q
0.05 (0.002)  
STYLE 1:  
STYLE 2:  
PIN 1.
 
SOURCE 1  
2. GATE
 
1  
STYLE 3:  
STYLE 4:  
STYLE 5:  
STYLE 6:  
PIN 1.
 
ANODE  
2. DRAIN  
PIN 1.
 
DRAIN  
2. DRAIN  
3. DRAIN  
4. GATE  
PIN 1.
 
ANODE  
2. ANODE  
3. SOURCE  
4. GATE  
PIN 1.
 
COLLECTOR  
2. COLLECTOR  
3. COLLECTOR  
4. BASE  
PIN 1.
 
ANODE  
2. ANODE  
3. DRAIN  
3. SOURCE
 
2  
4. GATE
 
2  
5. DRAIN
 
2  
6. DRAIN
 
2  
7. DRAIN
 
1  
8. DRAIN
 
1  
3. DRAIN  
4. GATE  
5. SOURCE  
6. DRAIN  
7. DRAIN  
8. CATHODE
 
/ DRAIN  
4. DRAIN  
5. SOURCE  
6. GATE  
7. CATHODE  
8. CATHODE  
5. SOURCE  
6. DRAIN  
7. DRAIN  
8. DRAIN  
5. DRAIN  
6. DRAIN  
7. CATHODE  
8. CATHODE  
5. EMITTER  
6. COLLECTOR  
7. COLLECTOR  
8. COLLECTOR  
SOLDERING FOOTPRINT  
GENERIC  
MARKING DIAGRAM*  
2.032  
0.08  
1
xxx M
G  
G
xxx  
M
= Specific Device Code  
= Month Code  
G
= Pb
−
Free Package  
(Note: Microdot may be in either location)  
2.362  
0.093  
0.65  
0.025  
PITCH  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”,  
may or may not be present.  
8X  
0.66  
0.026  
0.457  
0.018  
8X  
mm  
inches  
ǒ
Ǔ
Basic Style  
OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON03078D  
ChipFET  
PAGE 1 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

ChipFET
t  
CASE 1206A
−
03  
ISSUE K  
DATE 19 MAY 2009  
ADDITIONAL SOLDERING FOOTPRINTS*  
2.032  
0.08  
2.032  
0.08  
1
1
0.457  
0.018  
4X  
2X  
1.092  
0.043  
1.727  
0.068  
2.362  
0.093  
2.362  
0.093  
0.65  
0.025  
PITCH  
4X  
0.66  
0.026  
2X  
2X  
1.118  
0.044  
0.457  
0.018  
0.66  
0.026  
2X  
mm  
inches  
ǒ
Ǔ
mm  
inches  
ǒ
Ǔ
Styles 1 and 4  
Style 2  
2.032  
0.08  
2.032  
0.08  
2X  
2X  
0.66  
0.66  
0.026  
0.026  
1
1
1.092  
0.043  
1.092  
0.043  
2.362  
0.093  
2.362  
0.093  
0.65  
0.025  
PITCH  
0.65  
0.025  
PITCH  
1.118  
0.044  
1.118  
0.044  

2X

0.457  
0.018  

2X

0.457  
0.018  
mm  
inches  
mm  
inches  
ǒ
Ǔ
ǒ
Ǔ
Style 3  
Style 5  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON03078D  
ChipFET  
PAGE 2 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

onsemi
,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates  
and/or subsidiaries in the United States and/or other countries.
onsemi
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onsemi
’s product/patent coverage may be accessed at

.
onsemi
reserves the right to make changes at any time to any  
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−
is” and
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onsemi
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and applications using
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provided by
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onsemi
data sheets and/or specifications can and do vary in different applications and actual performance may  
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:  
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