onsemi-NTLJS4114NTAG
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NTLJS4114N
N-Channel,
m
Cool, WDFN,
2X2 mm
30
V
,
7
.8 A
Features
V
R
MAX
D
(BR)DSS
DS(on)
•
WDFN Package Provides Exposed Drain Pad for Excellent Thermal
Conduction
•
2×2 mm Footprint Same as SC
−
88
35 m
W
@ 4.5 V
45 m
W
@ 2.5 V
55 m
W
@ 1.8 V
30 V
7.8 A
•
Lowest R
•
1.8 V R
in 2×2 mm Package
Rating for Operation at Low
V
o
ltage Logic Level Gate
DS(on)
DS(on)
S
Drive
•
Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
•
This is a Pb
−
Free Device
G
Applications
•
DC
−
DC Conversion
•
Boost Circuits for LED Backlights
D
N
−
CHANNEL MOSFET
•
Optimized for Battery and Load Management Applications in
Portable Equipment such as, Cell Phones, PD
A
’s, Media Players, etc.
•
Low Side Load Switch for Noisy Environment
MARKING
DIAGRAM
S
D
WDFN6
CASE 506AP
STYLE 1
1
2
3
6
5
4
J
A
M
G
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
G
Pin 1
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
30
Unit
V
JA
M
G
= Specific Device Code
= Date Code
= Pb
−
Free Package
V
DSS
Gate
−
to
−
Source Voltage
V
GS
12
V
Continuous Drain
T =
25
°
C
I
D
6.0
A
(Note: Microdot may be in either location)
A
Steady
State
T =
85
°
C
A
4.4
PIN CONNECTIONS
t
≤
5 s
T =
25
°
C
A
7.8
Power Dissipation
Steady
State
P
1.92
W
D
D
D
G
D
D
S
1
2
3
6
5
4
T =
25
°
C
A
t
≤
5 s
3.3
3.6
D
Continuous Drain
T =
25
°
C
A
I
D
A
Steady
State
T =
85
°
C
A
2.6
S
Power Dissipation
P
D
0.70
W
T =
25
°
C
A
(
T
o
p View)
Pulsed Drain Current
t =
10
m
s
p
I
28
A
DM
ORDERING INFORMATION
Operating Junction and Storage
T
e
mperature
T , T
−
55 to
°
C
J
STG
150
†
Device
Package
Shipping
I
S
3.0
A
NTLJS4114NT1G
WDFN6
(Pb
−
Free)
WDFN6
3000/
T
a
pe & Reel
3000/
T
a
pe & Reel
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
NTLJS4114NTAG
(Pb
−
Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2019
−
Rev. 3
NTLJS4114N/D
NTLJS4114N
1. Surface
Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface
Mounted on FR4 Board using the minimum recommended pad size
of 30 mm2, 2 oz Cu.
2
NTLJS4114N
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
65
Unit
R
q
JA
R
38
°
C/W
q
JA
R
180
q
JA
3. Surface
Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
2
4. Surface
Mounted on FR4 Board using the minimum recommended pad size (30 mm
, 2 oz Cu).
MOSFET ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
= 250
m
A
30
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
I
D
= 250
m
A, Ref to 25
°
C
20
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
I
T =
25
°
C
1.0
10
m
A
DSS
J
V
DS
= 24
V
, V
= 0 V
GS
T =
85
°
C
J
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
12 V
100
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
0.4
0.55
3.18
1.0
V
GS(TH)
DS
D
Negative Gate Threshold
T
e
mperature Coefficient
V
/T
J
mV/
°
C
GS(TH)
Drain
−
to
−
Source On
−
Resistance
R
V
= 4.5
V
, I
= 2.0 A
20.3
25.8
35.2
8
35
45
55
m
W
DS(on)
GS
GS
GS
D
V
= 2.5
V
, I
= 2.0 A
D
V
= 1.8
V
, I
= 1.8 A
D
Forward Transconductance
g
FS
V
= 16 V, I
= 2.0 A
S
DS
D
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
650
115.5
70
pF
ISS
V
GS
= 0
V
, f =
1
.0 MHz,
Output Capacitance
Reverse Transfer Capacitance
T
o
tal Gate Charge
C
OSS
C
RSS
V
= 15 V
DS
Q
8.5
13
nC
G(TOT)
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
Gate Resistance
Q
0.6
G(TH)
V
GS
= 4.5
V
, V
= 15 V,
DS
I
= 2.0 A
D
Q
0.9
GS
Q
2.1
GD
R
3.0
W
G
Turn
−
On Delay Time
t
5
9
ns
d(ON)
Rise Time
t
r
V
= 4.5
V
, V
= 15 V,
GS
D
DD
I
= 2.0 A, R
= 3.0
W
G
Turn
−
Off Delay Time
t
20
4
d(OFF)
Fall Time
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Recovery Voltage
V
T =
25
°
C
0.71
0.58
14
1.2
35
SD
J
V
= 0
V
,
I
S = 2.0 A
V
GS
T =
85
°
C
J
Reverse Recovery Time
Charge Time
t
RR
t
8.0
6.0
5.0
ns
a
V
= 0
V
, d
/
d =
100 A/
m
s,
ISD t
GS
I =
1.0 A
S
Discharge Time
t
b
Reverse Recovery Time
Q
nC
RR
5. Pulse
T
e
st: Pulse Width
v
300
m
s, Duty Cycle
v
2%.
6. Switching
characteristics are independent of operating junction temperatures.
3
NTLJS4114N
TYPICAL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
7
8
V
GS
= 1.6 V to 8 V
V
DS
≥
10 V
T =
25
°
C
J
6
5
4
3
1.5 V
6
4
1.4 V
1.3 V
1.2 V
T =
25
°
C
J
2
1
0
2
0
T =
100
°
C
J
T =
−
55
°
C
J
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.03
0.025
0.02
0.05
0.04
0.03
0.02
T =
25
°
C
J
V
GS
= 4.5 V
T =
100
°
C
J
V
= 1.8 V
= 2.5 V
GS
T =
25
°
C
J
V
GS
T =
−
55
°
C
J
0.015
V
GS
= 4.5 V
0.01
0.01
0
0.005
1.0
1.5
2.0
2.5
3.0
1
2
3
4
5
6
I ,
DRAIN CURRENT (A)
D
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance versus Drain Current
Figure 4. On
−
Resistance versus Drain Current
and Gate Voltage
1.0E
−
04
1.0E
−
05
1.0E
−
06
1.6
1.4
1.2
1.0
V
GS
= 0 V
I
V
= 2 A
D
= 4.5 V
GS
T =
150
°
C
J
T =
125
°
C
J
T =
85
°
C
0.8
0.6
J
1.0E
−
07
−
50
−
25
0
25
50
75
100 125
150
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
T , JUNCTION TEMPERATURE (
°
C)
V
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
versus Voltage
4
NTLJS4114N
TYPICAL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
5
20
16
12
8
QT
1600
V
V
= 0 V
= 0 V
DS
GS
4
3
2
T =
25
°
C
J
V
DS
V
GS
C
iss
1000
400
Q
GD
Q
GS
C
oss
1
0
4
0
I
= 2 A
D
C
rss
T =
25
°
C
J
−
200
5
0
5
10
15
20
25
30
0
4
8
V
V
DS
GS
Q ,
TOTAL GATE CHARGE (nC)
G
GATE
−
TO
−
SOURCE OR DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
100
4
V
= 0 V
V
I
= 15 V
= 3.0 A
= 4.5 V
GS
DD
T =
25
°
C
J
D
V
GS
t
d(off)
3
2
1
t
f
t
r
t
d(on)
10
1
0
0.3
1
10
R ,
GATE RESISTANCE (OHMS)
100
0.4
0.5
0.6
0.7
0.8
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
100
See Note 2 on Page 1
10
m
s
10
1
100
m
s
1 ms
10 ms
SINGLE PULSE
= 25
°
C
T
C
T =
150
°
C
J
0.1
0.01
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
dc
0.1
1
10
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
5
NTLJS4114N
TYPICAL PERFORMANCE CURVES
(T =
25
°
C unless otherwise noted)
J
1000
100
D = 0.5
0.2
0.1
0.05
10
P
(pk)
0.02
0.01
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
1
READ TIME AT t
1
t
1
T
−
T =
P
R
q
(t)
JA
t
2
J(pk)
A
(pk)
SINGLE PULSE
0.0001
DUTY CYCLE, D = t
/t
1
2
0.1
0.000001
0.00001
0.001
0.01
t, TIME (s)
0.1
1
10
100
1000
Figure 12. Thermal Response
m
Cool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2×2
CASE 506AP
−
01
ISSUE B
DATE 26 APR 2006
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.20mm FROM
TERMINAL.
4. COPLANARITY
APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
1. CENTER
TERMINAL LEAD IS OPTIONAL. TERMINAL
LEAD IS CONNECTED TO TERMINAL LEAD # 4.
2. PINS
1, 2, 5 AND 6 ARE TIED TO THE FLAG.
SCALE 4:1
D
A
B
E
MILLIMETERS
PIN ONE
REFERENCE
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
A1
A3
b
0.20 REF
2X
0.10 C
0.25
0.51
0.35
0.61
b1
D
2.00 BSC
2X
0.10
C
1.00
1.20
1.30
D2
E
2.00 BSC
1.10
E2
e
A3
0.65 BSC
0.15 REF
0.10
C
K
L
0.20
0.20
0.30
0.30
L2
J
A
0.27 REF
0.65 REF
J1
7X
0.08
C
A1
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
C
4X
D2
1
2
3
6
5
4
e
L2
XX M
6X
L
1
3
XX =
Specific Device Code
= Date Code
b1
6X
M
0.10
0.05
C
C
A
B
E2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
NOTE 5
6
4
K
b
6X
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
0.10
0.05
C
C
A
B
J
J1
NOTE 3
2.30
BOTTOM VIEW
1.10
6X
6X
STYLE 1:
PIN 1.
DRAIN
2. DRAIN
STYLE 2:
0.35
0.43
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
3. GATE
1
4. SOURCE
5. DRAIN
6. DRAIN
4. EMITTER
5. COLLECTOR
6. COLLECTOR
0.60
1.25
0.34
0.35
0.66
0.65
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON20860D
6 PIN WDFN 2X2, 0.65P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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rights of others.
©
Semiconductor Components Industries, LLC, 2019
onsemi
,
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onsemi
” or its affiliates
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.
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−
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:
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