onsemi-NTLLD4901NFTWG
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NTLLD4901NF
N-Channel with Integrated
Schottky WDFN,
(3 mm x 3 mm)
30
V
,
H
igh Side 11 A / Low Side 13 A
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
Features
17.4 m
W
@ 10 V
25 m
W
@ 4.5 V
13.3 m
W
@ 10 V
20 m
W
@ 4.5 V
Q1
T
o
p FET
30 V
•
Co
−
Packaged Power Stage Solution to Minimize Board Space
•
Low Side MOSFET with Integrated Schottky
•
Minimized Parasitic Inductances
•
Optimized Devices to Reduce Power Losses
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
11 A
13 A
Q2 Bottom
FET 30 V
D1
(2, 3, 4, 9)
Applications
•
DC
−
DC Converters
•
System
V
o
ltage Rails
•
Point of Load
(1) G1
S1/D2 (10)
(8) G2
S2 (5, 6, 7)
PIN CONNECTIONS
D1 4
D1 3
D1 2
G1 1
5 S2
6 S2
7 S2
8 G2
9
D1
10
S1/D2
(Bottom View)
MARKING
DIAGRAM
1
4901
WDFN8
CASE 511BP
AYWW
G
1
G
4901
A
Y
= Specific Device Code
= Assembly Location
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
May, 2019
−
Rev. 1
NTLLD4901NF/D
NTLLD4901NF
MAXIMUM RATINGS
(T =
25
°
C unless otherwise stated)
J
Parameter
Symbol
Value
Unit
Drain
−
to
−
Source Voltage
Drain
−
to
−
Source Voltage
Gate
−
to
−
Source Voltage
Gate
−
to
−
Source Voltage
Q1
Q2
Q1
Q2
Q1
V
30
V
DSS
V
20
V
GS
Continuous Drain Current R
T =
25
°
C
I
D
8.3
6.0
q
JA
A
T =
85
°
C
A
A
T =
25
°
C
A
Q2
9.6
T =
85
°
C
A
6.9
Power Dissipation
T =
25
°
C
Q1
Q2
Q1
P
1.82
1.88
11
W
A
D
D
D
Continuous Drain Current R
T =
25
°
C
A
I
D
q
JA
T =
85
°
C
A
8
A
T =
25
°
C
A
Q2
13
Steady
State
T =
85
°
C
A
9.1
Power Dissipation
T =
25
°
C
A
Q1
Q2
Q1
P
3.23
3.27
5.5
W
R
q
JA
Continuous Drain Current
T =
25
°
C
A
I
D
R
q
JA
T =
85
°
C
A
4.0
A
T =
25
°
C
A
Q2
6.3
T =
85
°
C
A
4.5
Power Dissipation
T =
25
°
C
A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
P
0.80
0.81
65
W
A
R
q
JA
Pulsed Drain Current
TA = 25
°
C
tp = 10
m
s
I
DM
70
Operating Junction and Storage
T
e
mperature
Source Current (Body Diode)
T , T
−
55 to +150
°
C
A
J
STG
I
S
4.2
6.0
6
Drain to Source DV/DT
dV/dt
EAS
V/ns
mJ
Single Pulse Drain
−
to
−
Source Avalanche Energy (T
= 25C, V
= 50
V
,
Q1
Q2
12
J
DD
V
GS
= 10
V
, I
=
9
.0 A
, L = 0.3 mH, R
= 25
W
)
L pk
G
Single Pulse Drain
−
to
−
Source Avalanche Energy (T
= 25C, V
= 50
V
,
EAS
13.5
260
J
DD
V
GS
= 10
V
, I
=
9
.5 A
, L = 0.3 mH, R
= 25
W
)
L pk
G
Lead
T
e
mperature for Soldering Purposes
(1/8” from case for 10 s)
T
°
C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Surface
−
mounted on FR4 board using 1 sq
−
in pad, 2 oz Cu
2. Surface
−
mounted on FR4 board using the minimum recommended pad size of 90 mm
2
2
NTLLD4901NF
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
FET
Q1
Q2
Q1
Q2
Q1
Q2
Symbol
Value
68.8
Unit
R
q
q
q
JA
JA
JA
66.4
R
R
156.4
153.9
38.7
°
C/W
38.2
3. Surface
−
mounted on FR4 board using 1 sq
−
in pad, 2 oz Cu
4. Surface
−
mounted on FR4 board using the minimum recommended pad size of 90 mm
2
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
FET
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Break-
Q1
Q2
Q1
Q2
Q1
V
V
= 0
V
, I
=
2
50
m
A
30
30
V
(BR)DSS
GS
D
down Voltage
Drain
−
to
−
Source Break-
down Voltage
T
e
mperature
Coefficient
V
18
15
mV /
°
C
(BR)DSS
/ T
J
Zero Gate Voltage Drain
Current
I
V
= 0
V
,
= 24 V
T =
25
°
C
J
1
m
A
DSS
GS
DS
V
T =
125
°
C
J
10
Q2
V
= 0
V
,
= 24 V
T =
25
°
C
J
500
GS
DS
V
Gate
−
to
−
Source Leakage
Q1
Q2
I
V
= 0
V
,
V
DS =
20 V
100
100
nA
V
GSS
GS
Current
ON CHARACTERISTICS
(Note 5)
Gate Threshold Voltage
Q1
V
V
GS
= VDS, I
= 250
m
A
1.2
1.2
2.2
2.2
GS(TH)
D
Q2
Q1
Q2
Q1
Negative Threshold
T
e
mper-
ature Coefficient
V
/
4.5
4.0
14
20
11
mV /
°
C
GS(TH)
T
J
Drain
−
to
−
Source On Resist-
ance
R
V
= 10 V
= 4.5 V
= 10 V
= 4.5 V
I
I
= 9 A
= 9 A
17.4
25
DS(on)
GS
D
V
GS
D
m
W
Q2
V
I
= 11 A
= 11 A
13.3
20
GS
GS
D
D
V
I
16
16
18
Forward Transconductance
Q1
Q2
g
V
= 1.5
V
, I
= 9 A
S
FS
DS
D
CHARGES, CAPACITANCES & GATE RESISTANCE
Q1
605
660
190
325
102
17.5
Input Capacitance
Output Capacitance
Reverse Capacitance
C
ISS
Q2
Q1
Q2
Q1
Q2
C
OSS
C
RSS
V
GS
= 0
V
, f = 1
M
Hz, V
= 15 V
pF
DS
6.
Switching characteristics are independent of operating junction temperatures.
3
NTLLD4901NF
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
FET
Symbol
Test Condition
Min
Typ
Max
Unit
CHARGES, CAPACITANCES & GATE RESISTANCE
Q1
6.5
5.0
1.1
1.1
1.9
2.0
3.2
1.46
12
T
o
tal Gate Charge
Q
G(TOT)
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
Q
G(TH)
V
= 4.5
V
, V
=
1
5 V; I
= 9 A
nC
nC
GS
DS
D
Q
GS
GD
Q
Q
V
= 10
V
, V
=
1
5 V; I
= 9 A
GS DS
D
G(TOT)
10.6
SWITCHING CHARACTERISTICS
(Note 6)
Q1
8.0
7.5
7.2
11.2
11
Turn
−
On Delay Time
Rise Time
t
d(ON)
Q2
Q1
Q2
Q1
Q2
Q1
Q2
t
r
V
= 4.5
V
, V
=
1
5
V
,
DS
GS
D
ns
I
= 9 A, R
= 3.0
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
11.6
3.3
1.9
t
f
SWITCHING CHARACTERISTICS
(Note 6)
Q1
4.2
4.3
Turn
−
On Delay Time
Rise Time
t
d(ON)
Q2
Q1
Q2
Q1
Q2
Q1
Q2
11.6
11.4
14.1
14.3
2.0
t
r
V
= 10
V
, V
=
1
5
V
,
DS
GS
D
ns
I
= 9 A, R
= 3.0
W
G
Turn
−
Off Delay Time
Fall Time
t
d(OFF)
t
f
1.3
DRAIN
−
SOURCE DIODE CHARACTERISTICS
T =
25
°
C
0.80
0.65
0.50
0.45
1.2
J
V
= 0
V
,
GS
S
Q1
I
= 3 A
T =
125
°
C
J
Forward Voltage
V
SD
V
T =
25
°
C
J
0.80
V
GS
= 0
V
,
= 2 A
Q2
I
S
T =
125
°
C
J
6.
Switching characteristics are independent of operating junction temperatures.
4
NTLLD4901NF
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
FET
Symbol
Test Condition
Min
Typ
Max
Unit
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Q1
17.9
23.3
9.0
11.3
9.0
12
Reverse Recovery Time
Charge Time
t
RR
Q2
Q1
Q2
Q1
Q2
Q1
Q2
ta
ns
V
GS
= 0
V
, d
/
d =
100 A/
m
s, I
= 3 A
IS t
S
Discharge Time
tb
8.0
12
Reverse Recovery Charge
Q
nC
RR
PACKAGE PARASITIC VALUES
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
0.36
0.36
0.054
0.054
1.3
Source Inductance
Drain Inductance
Gate Inductance
Gate Resistance
L
nH
nH
nH
W
S
D
G
L
T =
25
°
C
A
L
1.3
0.8
R
G
0.8
5. Pulse
T
e
st: pulse width
≤
300
m
s, duty cycle
≤
2%
6. Switching
characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
NTLLD4901NFTWG
Package
Shipping
WDFN8
(Pb
−
Free)
3000 /
T
a
pe & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q1
30
10 V
25
3.6 V
4.5 V thru 4 V
3.4 V
3.8 V
V
DS
= 5 V
25
20
15
10
20
15
10
3.2 V
3.0 V
2.8 V
7.5 V
T =
125
°
C
J
T =
25
°
C
J
V
= 2.2 V
2.6 V
2.4 V
GS
5
0
5
0
T =
−
55
°
C
J
0
1
2
3
4
5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
23
22
21
20
19
18
17
16
15
55
V
= 4.5 V
GS
50
45
40
35
30
25
20
T = 25
°
C
I
D
= 10 A
V
GS
= 10 V
25
15
10
14
13
2
3
4
5
6
7
8
9
10
0
5
10
15
20
30
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Resistance
Gate Voltage
1E
−
05
1E
−
06
1E
−
07
1E
−
08
1E
−
09
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
I
V
= 9 A
D
T =
150
°
C
J
= 10 V
GS
T =
125
°
C
J
T =
25
°
C
J
1E
−
10
1E
−
11
0.6
0.5
−
50
−
25
0
25
50
75
100 125
150
0
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (
°
C)
J
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
6
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q1
10
800
700
600
500
400
300
200
QT
T =
25
°
C
GS
J
V
9
8
7
6
= 0 V
C
iss
5
4
3
2
1
0
Qgs
Qgd
C
oss
I
D
= 9 A
T =
25
°
C
J
C
rss
V
GS
V
DD
= 4.5 V
= 15 V
100
0
0
5
10
15
20
25
30
0
2
4
6
8
10
12
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
9
100
V
V
= 10 V
= 15 V
= 10 A
GS
V
GS
= 0 V
8
7
6
5
4
DD
I
D
T =
25
°
C
J
t
f
t
r
10
3
2
t
t
d(on)
d(off)
1
0
1
1
10
R ,
GATE RESISTANCE (
W
)
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1.1
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
V
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
10
1
14
12
10
8
I
= 9 A
D
10
m
s
100
m
s
1 ms
V
= 20 V
GS
6
SINGLE PULSE
= 25
°
C
10 ms
T
C
4
0.1
dc
R
LIMIT
DS(on)
2
0
THERMAL LIMIT
PACKAGE LIMIT
0.01
25 40
55
70
85 100 115
130 145
160
0.1
1
10
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
7
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q1
100
10
D = 0.5
0.2
0.1
0.05
0.02
0.01
1
SINGLE PULSE
0.00001 0.0001
0.1
0.000001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (sec)
Figure 13. Thermal Response
8
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q2
40
40
35
30
25
20
15
10
3.8 V
10 V
3.6 V
3.4 V
3.2 V
V
DS
= 5 V
35
30
25
20
15
10
4.5 thru 4.0 V
7.5 V
T =
25
°
C
J
3.0 V
2.8 V
V
= 2.2 V
GS
T =
125
°
C
2.6 V
2.4 V
J
5
0
5
0
T =
−
55
°
C
J
0
1
2
3
4
5
1
0
0
1.5
2
2.5
3
3.5
4
4.5
40
30
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
, GATE
−
TO
−
SOURCE VOLTAGE (V)
DS
GS
Figure 14. On
−
Region Characteristics
Figure 15. Transfer Characteristics
60
20
18
16
14
12
I
D
= 10 A
T = 25
°
C
V
= 4.5 V
50
GS
40
30
20
10
0
V
GS
= 10 V
10
8
2
3
4
5
6
7
8
9
10
5
10
15
20
25
30
35
V
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
GS
D
Figure 16. On
−
Resistance vs. Gate
−
to
−
Source
Figure 17. On
−
Resistance vs. Drain Current
Resistance
and Gate Voltage
1E
−
02
1.6
1.4
1.2
1.0
I
= 11 A
D
T =
150
°
C
J
V
GS
= 10 V
T =
125
°
C
J
1E
−
03
1E
−
04
T =
25
°
C
J
1E
−
05
1E
−
06
0.8
0.6
V
= 0 V
GS
−
50
−
25
0
25
50
75
100 125
150
5
10
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
15
20
25
T , JUNCTION TEMPERATURE (
°
C)
J
V
Figure 18. On
−
Resistance Variation with
Figure 19. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
9
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q2
10
QT
1000
100
C
9
8
7
6
iss
C
C
oss
5
4
3
2
1
0
Qgs
Qgd
rss
I
D
= 9 A
10
1
T =
25
°
C
J
V
GS
V
DD
= 4.5 V
= 15 V
T =
25
°
C
GS
J
V
= 0 V
0
5
10
15
20
25
30
0
2
4
6
8
10
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 20. Capacitance Variation
Figure 21. Gate
−
to
−
Source and
Drain
−
to
−
Source Voltage vs. Total Charge
8
7
6
5
4
3
2
100
V
= 10 V
= 15 V
= 10 A
GS
V
= 0 V
V
DD
GS
I
D
T =
25
°
C
J
t
d(off)
t
r
10
t
d(on)
1
0
t
f
1
1
10
R ,
GATE RESISTANCE (
W
)
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
V
SD
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
G
Figure 22. Resistive Switching Time Variation
vs. Gate Resistance
Figure 23. Diode Forward Voltage vs. Current
100
10
1
14
12
10
8
I
= 9.5 A
10
m
s
D
100
m
s
1 ms
0 V < V
< 20 V
SINGLE PULSE
GS
6
10 ms
T
C
= 25
°
C
4
0.1
dc
R
LIMIT
DS(on)
2
0
THERMAL LIMIT
PACKAGE LIMIT
0.01
25 40
55
70
85 100 115
130 145
160
0.1
1
10
100
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
T , STARTING JUNCTION TEMPERATURE (
°
C)
J
Figure 24. Maximum Rated Forward Biased
Safe Operating Area
Figure 25. Maximum Avalanche Energy vs.
Starting Junction Temperature
10
NTLLD4901NF
TYPICAL CHARACTERISTICS
−
Q2
100
10
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (sec)
Figure 26. Thermal Response
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3×3, 0.65P
CASE 511BP
ISSUE B
1
DATE 17 JUL 2012
SCALE 2:1
NOTES:
A
B
E
D
L
L
1. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
3. DIMENSION
b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.05 AND 0.15 MM FROM TERMINAL TI
P
.
4. COPLANARITY
APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL
TOLERANCE APPLIES TO ALL
OF THE EXPOSED PADS.
L1
DETAIL A
PIN ONE
REFERENCE
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
0.15
C
A3
DIM MIN
MAX
0.80
0.05
EXPOSED Cu
MOLD CMPD
A
A1
A3
b
D
D2
E
E2
E3
e
G
G2
K
0.70
0.00
0.15
C
TOP VIEW
0.20 REF
0.30
0.50
A
3.00 BSC
DETAIL B
A1
0.10
C
2.35
2.55
A3
C
DETAIL B
3.00 BSC
ALTERNATE
0.90
0.40
1.10
0.60
CONSTRUCTIONS
0.08
C
0.65 BSC
0.43 BSC
0.68 BSC
A1
SEATING
PLANE
NOTE 4
SIDE VIEW
D2
0.20
0.20
0.00
−−−
0.40
0.15
L
L1
M
0.10
C A B
DETAIL A
NOTE 5
1
GENERIC
MARKING DIAGRAM*
4
K
E3
G2
1
XXXX
AYWW
G
G
M
0.10
C A B
G
NOTE 5
XXXX =
Specific Device Code
E2
8
5
A
Y
= Assembly Location
=
Y
e
ar
= Work Week
8X
b
e
M
M
0.10
C
C
A
B
WW
G
e/2
0.05
NOTE 3
= Pb
−
Free Package
BOTTOM VIEW
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking.
RECOMMENDED
SOLDERING FOOTPRINT*
2.60
1.88
1.80
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
5X
0.50
STYLE 1:
PIN 1.
GATE 1
0.43
0.68
2. DRAIN
1
3. DRAIN
1
4. DRAIN
1
5. SOURCE
2
6. SOURCE
2
7. SOURCE
2
8. GATE
2
1.15
3.30
9. DRAIN
1
10. SOURCE
1/DRAIN 2
0.65
1
6X
0.65
PITCH
0.50
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER:
DESCRIPTION:
98AON53342E
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
WDFN8, 3X3, 0.65P
PAGE 1 OF 1
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