onsemi-NTMFS4C59NT1G

Part #onsemi-NTMFS4C59NT1G
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onsemi-NTMFS4C59NT1G
NTMFS4C59N  
Power MOSFET  
30
V
,
5
2 A, Single N
−
Channel, SO
−
8 FL  
Features  
•
Low R  
to Minimize Conduction Losses  
•
Low Capacitance to Minimize Driver Losses  
DS(on)  
•
Optimized Gate Charge to Minimize Switching Losses  
•
These Devices are Pb
−
Free and are RoHS Compliant  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(ON)  
Applications  
5.8 m
W
@ 10 V  
8.5 m
W
@ 4.5 V  
•
CPU Power Delivery  
•
DC
−
DC Converters  
30 V  
52 A  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise stated)  
J
D (5
−
8)  
Parameter  
Drain
−
to
−
Source Voltage  
Gate
−
to
−
Source Voltage  
Symbol  
Value  
30  
Unit  
V
V
DSS  
V
GS  
20  
V
G (4)  
Continuous Drain  
Current R  
T =
 
25
°
C  
I
16.4  
A
A
D
q
JA  
T =
 
80
°
C  
A
12.3  
2.51  
S (1,2,3)  
N
−
CHANNEL MOSFET  
Power Dissipation  
T =
 
25
°
C  
A
P
W
A
D
D
D
D
R
q
JA  
Continuous Drain  
T =
 
25
°
C  
A
I
D
25.3  
19.0  
6.0  
MARKING  
DIAGRAM  
Current R  
≤
10 s  
q
JA  
T =
 
80
°
C  
A
Power Dissipation  
≤
10 s

)  
T =
 
25
°
C  
A
P
W
A
D
R
q
JA  
Steady  
State  
S
S
S
G
D
D
1
Continuous Drain  
Current R  
T =
 
25
°
C  
A
I
D
9.0  
6.8  
4C59N  
AYWZZ  
q
JA  
SO
−
8 FLAT LEAD  
CASE 488AA  
STYLE 1  
T =
 
80
°
C  
A
Power Dissipation  
T =
 
25
°
C  
A
P
0.76  
W
A
D
R
q
JA  
Continuous Drain  
Current R  
T
= 25
°
C  
=80
°
C  
= 25
°
C  
I
D
52  
39  
C
A
Y
W
ZZ  
= Assembly Location  
=
Y
e
ar  
= Work Week  
= Lot Traceabililty  
q
JC  
T
C
C
Power Dissipation  
T
P
25.5  
W
A
R
q
JC  
Pulsed Drain  
Current  
T =
 
25
°
C, t
 
= 10
m
s  
I
DM  
146  
80  
A
p
ORDERING INFORMATION  
Current Limited by Package  
T =
 
25
°
C  
A
I
A
Dmax  
†
Operating Junction and Storage  
T
e
mperature  
T ,  
STG  
−
55 to  
°
C  
Device  
Package  
Shipping  
J
T
+150  
NTMFS4C59NT1G  
SO
−
8 FL  
(Pb
−
Free)  
1500 /  
Source Current (Body Diode)  
Drain to Source dV/dt  
I
S
23  
7.0  
42  
A
T
a
pe & Reel  
dV/d  
V/ns  
mJ  
t
NTMFS4C59NT3G  
SO
−
8 FL  
(Pb
−
Free)  
5000 /  
Single Pulse Drain
−
to
−
Source Avalanche  
Energy (T
 
= 25
°
C, V
 
= 10
V
, I
 
=
2
9 A
 
,  
pk  
E
AS  
T
a
pe & Reel  
J
GS  
L
L = 0.1 mH, R
 
= 25
W

†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our
T
a
pe and Reel Packaging Specifications  
Brochure, BRD8011/D.  
GS  
Lead
T
e
mperature for Soldering Purposes  
(1/8
″
from case for 10 s)  
T
L
260  
°
C  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Surface
−
mounted on FR4 board using 1 sq
−
in pad, 1 oz Cu.  
2. Surface
−
mounted on FR4 board using the minimum recommended pad size.  
3. Parts
 
are 100% tested at T
 
= 25
°
C, V
 
= 10
V
, I
 
=
2
0 A
 
, EAS = 20 mJ.  
J
GS  
L
pk  
©
Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
March, 2013
−
Rev. 0  
NTMFS4C59N/D  
 

NTMFS4C59N  
THERMAL RESISTANCE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
4.9  
Unit  
Junction
−
to
−
Case (Drain)  
R
q
JC  
Junction
−
to
−
Ambient – (t
≤

R
49.8  
164.6  
21.0  
q
JA  
°
C/W  
R
q
JA  
R
q
JA  
4. Surface
−
mounted on FR4 board using 1 sq
−
in pad, 1 oz Cu.  
5. Surface
−
mounted on FR4 board using the minimum recommended pad size.  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise specified)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain
−
to
−
Source Breakdown Voltage  
V
V
= 0
V
, I
 
=
2
50
m
A  
30  
34  
V
V
(BR)DSS  
GS  
D
Drain
−
to
−
Source Breakdown Voltage  
(transient)  
V
V
= 0
V
, I  
= 8.4 A,  
= 100 ns  
(BR)DSSt  
GS  
case  
D(aval)  
T
= 25
°
C, t  
transient  
Drain
−
to
−
Source Breakdown Voltage  
T
e
mperature Coefficient  
V
/
14.4  
(BR)DSS  
mV/
°
C  
T
J
Zero Gate Voltage Drain Current  
I
V
= 0
V
,  
= 24 V  
T =
 
25
°
C  
1.0  
10  
DSS  
GS  
DS  
J
V
m
A  
T =
 
125
°
C  
J
Gate
−
to
−
Source Leakage Current  
ON CHARACTERISTICS

Gate Threshold Voltage  
I
V
= 0
V
, V  
=
20 V  
100  
nA  
GSS  
DS  
GS  
V
V
= V
 
, I
 
= 250
m
A  
1.3  
2.1  
V
GS(TH)  
GS  
DS  
D
Negative Threshold
T
e
mperature Coefficient  
Drain
−
to
−
Source On Resistance  
V
/T  
4.8  
4.6  
6.8  
50  
mV/
°
C  
GS(TH)  
J
R
V
= 10 V  
I
I
= 30 A  
= 18 A  
5.8  
8.5  
DS(on)  
GS  
D
m
W  
V
GS  
= 4.5 V  
D
Forward Transconductance  
Gate Resistance  
g
FS  
V
= 1.5
V
, I
 
=
1
5 A  
S
DS  
D
R
T =
 
25
°
C  
A
1.0  
W
G
CHARGES AND CAPACITANCES  
Input Capacitance  
C
1252  
610  
126  
0.101  
10.9  
1.9  
ISS  
Output Capacitance  
C
V
= 0
V
, f = 1
M
Hz, V
 
= 15 V  
pF  
nC  
OSS  
RSS  
GS  
DS  
Reverse Transfer Capacitance  
Capacitance Ratio  
C
C
/C  
V
GS  
= 0
V
, V
 
=
1
5
V
, f = 1
M
Hz  
RSS ISS  
DS  
T
o
tal Gate Charge  
Q
G(TOT)  
Threshold Gate Charge  
Gate
−
to
−
Source Charge  
Gate
−
to
−
Drain Charge  
Gate Plateau Voltage  
T
o
tal Gate Charge  
Q
G(TH)  
Q
3.4  
V
GS  
= 4.5
V
, V
 
=
1
5 V; I
 
= 30 A  
GS  
GD  
GP  
DS  
D
Q
V
5.4  
3.1  
V
Q
V
GS  
= 10
V
, V
 
=
1
5 V; I
 
= 30 A  
22.2  
nC  
G(TOT)  
DS  
D
SWITCHING CHARACTERISTICS

Turn
−
On Delay Time  
Rise Time  
t
10  
32  
16  
6.0  
d(ON)  
t
r
V
= 4.5
V
, V
 
=
1
5
V
,  
DS  
GS  
D
ns  
I
= 15 A, R
 
= 3.0
W  
G
Turn
−
Off Delay Time  
Fall Time  
t
d(OFF)  
t
f

6.

Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.  

7.

Switching characteristics are independent of operating junction temperatures.  
2
 

NTMFS4C59N  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise specified)  
J
Parameter  
SWITCHING CHARACTERISTICS

Turn
−
On Delay Time  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
t
7.0  
28  
d(ON)  
Rise Time  
t
r
V
= 10
V
, V
 
=
1
5
V
,  
DS  
GS  
D
ns  
I
= 15 A, R
 
= 3.0
W  
G
Turn
−
Off Delay Time  
t
20  
d(OFF)  
Fall Time  
t
f
4.0  
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
T =
 
25
°
C  
0.79  
0.65  
31  
1.1  
SD  
RR  
J
V
S
= 0
V
,  
GS  
V
I
= 10 A  
T =
 
125
°
C  
J
Reverse Recovery Time  
Charge Time  
t
t
15  
ns  
a
V
= 0
V
,
d
IS/dt = 100 A/
m
s,  
GS  
I
S
= 30 A  
Discharge Time  
t
16  
b
Reverse Recovery Charge  
Q
15  
nC  
RR  
6. Pulse
 
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.  
7. Switching
 
characteristics are independent of operating junction temperatures.  
3
 

NTMFS4C59N  
TYPICAL CHARACTERISTICS  
100  
90  
80  
70  
60  
50  
40  
30  
20  
100  
4.5 V to 10 V  
4.0 V  
90  
80  
70  
60  
50  
40  
30  
20  
V
= 5 V  
DS  
T =
 
25
°
C  
J
3.8 V  
3.6 V  
3.4 V  
3.2 V  
3.0 V  
T =
 
125
°
C  
J
2.8 V  
= 2.6 V  
10  
0
10  
0
T =
 
−
55
°
C  
J
V
T =
 
25
°
C  
J
GS  
0
1
2
3
4
5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
 
5.5  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
V
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
V
GS  
DS  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
0.026  
0.024  
0.022  
0.020  
0.018  
0.016  
0.014  
0.009  
0.008  
0.007  
0.006  
0.005  
I
= 30 A  
T =
 
25
°
C  
D
J
V
= 4.5 V  
GS  
0.012  
0.010  
0.008  
0.006  
0.004  
0.002  
V
= 10 V  
GS  
0.004  
0.003  
3
4
5
6
7
8
9
10  
10  
20  
30  
40  
50  
60  
70  
V
GS  
, GATE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source  
Figure 4. On
−
Resistance vs. Drain Current and  
Voltage  
Gate Voltage  
1600  
1.7  
1.6  
1.5  
V
= 0 V  
GS  
V
= 10 V  
= 30 A  
GS  
1400  
1200  
1000  
800  
T =
 
25
°
C  
J
C
iss  
I
D
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
C
C
oss  
600  
400  
rss  
200  
0
0.8  
0.7  
−
50
−
25  
0
25  
50  
75  
100 125  
150  
0
5
10  
15  
20  
25  
30  
T , JUNCTION TEMPERATURE (
°
C)  
J
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Figure 5. On
−
Resistance Variation with  
Figure 6. Capacitance Variation  
Temperature  
4

NTMFS4C59N  
TYPICAL CHARACTERISTICS  
10  
8
1000  
V
GS  
V
DD  
= 10 V  
= 15 V  
Q
T
I
D
= 15 A  
t
d(off)  
100  
t
f
6
4
t
r
Q
Q
GD  
GS  
10  
1
t
d(on)  
V
V
= 10 V  
= 15 V  
= 30 A  
GS  
DD  
2
0
I
D
T =
 
25
°
C  
J
0
2
4
6
8
10 12 14 16 18 20 22 24  
1
10  
R ,
 
GATE RESISTANCE (
W
)  
100  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
G
Figure 7. Gate
−
to
−
Source and  
Drain
−
to
−
Source Voltage vs. Total Charge  
Figure 8. Resistive Switching Time Variation  
vs. Gate Resistance  
20  
18  
16  
1000  
100  
10  
0 V < V
 
< 10 V  
GS  
V
GS  
= 0 V  
10
m
s  
14  
12  
10  
8
100
m
s  
T =
 
25
°
C  
J
T =
 
125
°
C  
J
1 ms  
10 ms  
1
6
4
R
Limit  
DS(on)  
0.1  
dc  
Thermal Limit  
Package Limit  
2
0
0.01  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
0.01  
0.1  
1
10  
100  
V
SD  
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
Figure 9. Diode Forward Voltage vs. Current  
Figure 10. Maximum Rated Forward Biased  
Safe Operating Area  
80  
70  
60  
50  
40  
30  
20  
20  
18  
16  
14  
12  
10  
8
I
D
= 20 A  
6
4
10  
0
2
0
25  
50  
75  
100  
125  
150  
0
5
10 15 20 25 30 35 40 45 50  
(A)  
T , STARTING JUNCTION TEMPERATURE (
°
C)  
I
D
J
Figure 11. Maximum Avalanche Energy vs.  
Starting Junction Temperature  
Figure 12. G

FS

vs. I

D  

5

NTMFS4C59N  
TYPICAL CHARACTERISTICS  
100  
10  
1
1.E
−
08 1.E
−
07  
1.E
−
06  
1.E
−
05  
1.E
−
04  
1.E
−
03  
PULSE WIDTH (sec)  
Figure 13. Avalanche Characteristics  
100  
10  
1
Duty Cycle = 0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
0.1  
Single Pulse  
0.01  
0.000001 0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 14. Thermal Response  
6

NTMFS4C59N  
PACKAGE DIMENSIONS  
DFN5 5×6, 1.27P (SO8 FL)  
CASE 488AA  
ISSUE H  
2 X  
NOTES:  
1. DIMENSIONING
 
AND TOLERANCING PER  
ASME Y14.5M, 1994.  
0.20  
C
2. CONTROLLING
 
DIMENSION: MILLIMETER.  
3. DIMENSION
 
D1 AND E1 DO NOT INCLUDE  
MOLD FLASH PROTRUSIONS OR GATE  
BURRS.  
D
A
2
B
E
2 X  
D1  
MILLIMETERS  
0.20  
C
DIM  
A
A1  
b
MIN  
0.90  
0.00  
0.33  
0.23  
NOM  
1.00  
−−−  
0.41  
0.28  
MAX  
1.10  
0.05  
0.51  
0.33  
4 X  
q
E1  
2
c
D
5.15 BSC  
4.90  
4.00  
6.15 BSC  
5.90  
3.65  
D1  
D2  
E
E1  
E2  
e
4.70  
3.80  
5.10  
4.20  
c
A1  
5.70  
3.45  
6.10  
3.85  
1
2
3
4
1.27 BSC  
G
K
L
L1  
M
0.51  
1.20  
0.51  
0.05  
3.00  
0
0.61  
1.35  
0.61  
0.17  
3.40  
−−−  
0.71  
1.50  
0.71  
0.20  
3.80  
TOP VIEW  
C
3 X  
e
SEATING  
PLANE  
0.10  
0.10  
C
C
DETAIL A  
q
12  
A
_
_
SOLDERING FOOTPRINT*  
SIDE VIEW  
DETAIL A  
STYLE 1:  
3X  
4X  
PIN 1.
 
SOURCE  
2. SOURCE  
3. SOURCE  
4. GATE  
1.270  
0.750  
4X  
1.000  
b
8X  
0.10  
0.05  
C
c
A
B
5. DRAIN  
6. DRAIN  
e/2  
L
0.965  
1
4
0.

2

9

X

05  
0.475  
1.330  
K
2X  
0.495  
4.530  
E2  
PIN 5  
(EXPOSED PAD)  
M
3.200  
L1  
2X  
1.530  
D2  
BOTTOM VIEW  
G
4.560  
*For additional information on our Pb
−
Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.  
ON Semiconductor
and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
 
SCILLC owns the rights to a number of patents, trademarks,  
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at

. SCILLC  
reserves the right to make changes without further notice to any products herein.
 
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any  
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without  
limitation special, consequential or incidental damages.
 
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications  
and actual performance may vary over time.
 
All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
 
SCILLC  
does not convey any license under its patent rights nor the rights of others.
 
SCILLC products are not designed, intended, or authorized for use as components in systems intended for  
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where  
personal injury or death may occur.
 
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and  
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,  
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture  
of the part.
 
SCILLC is an Equal Opportunity/Affirmative Action Employer.
 
This literature is subject to all applicable copyright laws and is not for resale in any manner.  
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