onsemi-NTMFSC4D2N10MC

Part #onsemi-NTMFSC4D2N10MC
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onsemi-NTMFSC4D2N10MC

MOSFET

– Powe
r
,
S
ingle  
N-Channel, DUAL COOL
t
,  
100
V
,
4
.3 m
W
, 116 A  
DFN8 5×6.15  
NTMFSC4D2N10MC  
Features  
•
Advanced Dual
−
Sided Cooled Packaging  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(ON)  
•
Ultra Low R  
to Minimize Conduction Losses  
DS(on)  
4.3 m
W
@ 10 V  
12 m
W
@ 6 V  
•
MSL1 Robust Packaging Design  
100 V  
116 A  
•
175
°
C T
 
Capable  
J
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS  
Compliant  
N
−
Channel MOSFET  
Typical Applications  
S
S
S
1
8
D
D
D
•
Orring FET/Load Switching  
•
Synchronous Rectifier  
•
DC
−
DC Conversion  
2
3
7
6
MAXIMUM RATINGS
(T =
 
25
°
C, Unless otherwise specified)  
J
Parameter  
Drain
−
to
−
Source Breakdown Voltage  
Gate
−
to
−
Source Voltage  
Symbol  
Value  
100  
20  
Unit  
V
G
4
5
D
V
(BR)DSS  
V
GS  
V
Continuous Drain  
Current R  
I
116  
A
D
q
JC  
Steady  
State  
T
= 25
°
C  
C
Power Dissipation  
P
122  
W
A
D
R
q
JC  
Continuous Drain  
Current R  
I
D
29.6  
q
JA  
DFN8 5×6.15  
CASE 506EG  
Steady  
State  
T =
 
25
°
C  
A
Power Dissipation  
P
7.9  
W
A
D
R
q
JA  
Pulsed Drain Cur-  
rent  
T =
 
25
°
C, t
 
= 10
m
s  
A
I
DM  
900  
MARKING DIAGRAM  
p
AYWWZZ  
4D2N10  
Operating Junction and Storage
T
e
mpera-  
ture  
T , T  
−
55 to  
+175  
°
C  
J
stg  
Source Current (Body Diode)  
I
101  
120  
A
S
Single Pulse Drain
−
to
−
Source Avalanche  
E
AS  
mJ  
Energy (I
 
= 49 A, L = 0.1 mH)  
AV  
Lead
T
e
mperature Soldering Reflow for Sol-  
dering Purposes (1/8” from case for 10 s)  
T
L
300  
°
C  
4D2N10 = Specific Device Code  
A
Y
= Assembly Location  
=
Y
e
ar  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
WW =
 
Work Week  
ZZ  
2
1. Surface
−
mounted on FR4 board using 1 in
 
pad size, 1 oz Cu pad.  
= Assembly Lot Code  
2. The
 
entire application environment impacts the thermal resistance values shown,  
they are not constants and are only valid for the particular conditions noted.  
ORDERING INFORMATION  
this data sheet.  
©
Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
July, 2020
−
Rev. 2  
NTMFSC4D2N10MC/D  
 

NTMFSC4D2N10MC  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Max  
1.23  
19  
Unit  
°
C/W  
R
q
JC  
JA  
R
q
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain
*
to
*
Source Breakdown Voltage  
V
V
= 0
V
, I
 
=
2
50
m
A  
100  
V
(BR)DSS  
GS  
D
Drain
*
to
*
Source Breakdown Voltage  
V
/ T  
8.5  
mV/
°
C  
(BR)DSS  
J
I
D
= 250
m
A, ref to 25
°
C  
T
e
mperature Coefficient  
Zero Gate Voltage Drain Current  
I
T =
 
25
°
C  
1
m
A  
DSS  
J
V
GS  
= 0 V
,
V =
 
100 V  
DS  
T =
 
125
°
C  
J
100  
100  
Gate
*
to
*
Source Leakage Current  
ON CHARACTERISTICS

Gate Threshold Voltage  
I
V
DS  
= 0
V
, V
 
=  
GS  
20 V  
nA  
GSS  
V
V
GS  
= V
 
, I
 
= 250
m
A  
2.0  
4.0  
V
GS(TH)  
DS  
D
V
/ T  
Negative Threshold
T
e
mperature  
Coefficient  
−
9.4  
mV/
°
C  
GS(TH)  
J
I
D
= 250
m
A, ref to 25
°
C  
R
Drain
*
to
*
Source On Resistance  
V
= 10 V, I
 
= 44 A  
3.7  
6.0  
1.2  
4.3  
12  
m
W  
W
DS(on)  
GS  
D
V
= 6
V
, I
 
= 22 A  
D
GS  
Gate
−
Resistance  
R
T =
 
25
°
C  
A
G
CHARGES & CAPACITANCES  
Input Capacitance  
C
2856  
1670  
29  
pF  
ISS  
C
C
Output Capacitance  
Reverse Transfer Capacitance  
T
o
tal Gate Charge  
V
= 0
V
, f = 1
M
Hz, V
 
= 50 V  
DS  
OSS  
RSS  
GS  
Q
V
= 6
V
, V
 
=
5
0
V
, I
 
=
4
4 A  
27  
nC  
G(TOT)  
GS  
DS  
D
Q
T
o
tal Gate Charge  
42  
G(TOT)  
Q
Gate
−
to
−
Source Charge  
Gate
−
to
−
Drain Charge  
Plateau Voltage  
12  
GS  
V
GS  
= 10
V
, V
 
=
5
0
V
, I
 
=
4
4 A  
DS D  
Q
12  
GD  
V
4.9  
V
GP  
SWITCHING CHARACTERISTICS

Turn
*
On Delay Time  
Rise Time  
t
d(ON)  
12  
18  
30  
5.2  
ns  
t
r
V
GS  
= 10
V
, V
 
=
5
0 V
,  
DS  
D G  
t
I =
 
44 A, R
 
= 2.5
W  
Turn
*
Off Delay Time  
Fall Time  
d(OFF)  
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
0.85  
0.73  
65.5  
100  
V
T =
 
25
°
C  
J
SD  
J
V
GS  
= 0
V
, I
 
=
4
4 A  
S
T =
 
125
°
C  
Reverse Recovery Time  
t
ns  
RR  
V
GS  
= 0
V
,
d
I
 
/dt = 100 A/
m
s,  
S
I
= 44 A  
S
Reverse Recovery Charge  
Q
nC  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
3. Switching
 
characteristics are independent of operating junction temperatures.  
2
 

NTMFSC4D2N10MC  
TYPICAL CHARACTERISTICS  
100  
90  
80  
70  
60  
50  
40  
30  
20  
140  
5.6 V  
5.4 V  
= 10 V to 7 V  
V
DS  
= 10 V  
120  
100  
80  
V
GS  
5.2 V  
5.0 V  
60  
40  
20  
0
4.8 V  
4.6 V  
T =
 
25
°
C  
J
4.4 V  
4.2 V  
10  
0
T =
 
125
°
C  
J
T =
 
−
55
°
C  
J
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
0
1
2
3
4
5
6
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
V
GS  
, GATE
−
TO
−
SOURCE VOLTAGE (V)  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
8.0  
7.0  
6.0  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
T =
 
25
°
C  
D
T =
 
25
°
C  
J
J
I
= 44 A  
V
GS  
= 6 V  
5.0  
4.0  
3.0  
2.0  
V
GS  
= 10 V  
65  
4
5
6
7
8
9
10  
0
25  
45  
85  
105  
125  
V
GS  
, GATE VOLTAGE (V)  
I ,
 
DRAIN CURRENT (A)  
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source  
Figure 4. On
−
Resistance vs. Drain Current and  
Voltage  
Gate Voltage  
2.2  
1.E+05  
1.E+04  
V
= 10 V  
= 44 A  
GS  
2.0  
1.8  
1.6  
I
D
T =
 
150
°
C  
J
T =
 
125
°
C  
J
1.E+03  
1.E+02  
1.4  
1.2  
1.0  
0.8  
0.6  
T =
 
85
°
C  
J
1.E+01  
1.E+00  
−
50
−
25  
0
25  
50  
75 100
 
125 150 175  
5
15  
25  
V ,
 
DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
DS  
35  
45  
55  
65  
75  
85  
95  
T , JUNCTION TEMPERATURE (
°
C)  
J
Figure 5. On
−
Resistance Variation with  
Figure 6. Drain
−
to
−
Source Leakage Current  
Temperature  
vs. Voltage  
3

NTMFSC4D2N10MC  
TYPICAL CHARACTERISTICS  
10,000  
1000  
10  
C
ISS  
9
8
7
6
5
4
3
2
C
OSS  
Q
Q
GD  
GS  
100  
10  
1
C
RSS  
V
= 0 V  
V
I
= 50 V  
= 44 A  
GS  
DS  
T =
 
25
°
C  
J
D
1
0
f = 1 MHz  
T =
 
25
°
C  
J
0
10 20 30 40 50 60 70 80 90
 
100  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
V
DS  
Q ,
 
TOTAL GATE CHARGE (nC)  
G
Figure 7. Capacitance Variation  
Figure 8. Gate
−
to
−
Source and  
Drain
−
to
−
Source Voltage vs. Total Charge  
100  
10  
1
1000  
V
V
= 10 V  
= 50 V  
= 44 A  
V
= 0 V  
GS  
GS  
DS  
I
D
t
d(off)  
t
f
100  
10  
1
t
r
t
d(on)  
T =
 
125
°
C  
J
T =
 
25
°
C  
T =
 
−
55
°
C  
J
J
0.1  
0.3  
1
10  
R ,
 
GATE RESISTANCE (
W
)  
100  
0.4  
0.5  
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)  
SD  
0.6  
0.7  
0.8  
0.9  
1
V
G
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
100  
1000  
100  
T
= 25
°
C  
J(initial)  
10  
1
10  
T
= 100
°
C  
J(initial)  
V
≤
10 V  
GS  
10
m
s  
Single Pulse  
T
C
= 25
°
C  
1
0.5 ms  
1 ms  
R
Limit  
DS(on)  
Thermal Limit  
Package Limit  
10 ms  
0.1  
0.1  
0.1  
0.00001  
1
10  
100  
1000  
0.0001  
0.001  
0.01  
V
DS  
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)  
TIME IN AVALANCHE (s)  
Figure 11. Safe Operating Area  
Figure 12. I

PEAK

vs. Time in Avalanche  
4

NTMFSC4D2N10MC  
TYPICAL CHARACTERISTICS  
100  
10  
50% Duty Cycle  
20%  
10%  
5%  
1
2%  
1%  
0.1  
0.01  
Single Pulse  
0.001  
0.000001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 13. Thermal Characteristics  
ORDERING INFORMATION  
Device  
†
Device Marking  
4D2N  
Package  
Shipping  
NTMFSC4D2N10MC  
DFN8 5×6.15  
(Pb
−
Free/Halogen Free)  
3000 /
T
a
pe & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
DUAL COOL is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other coun-  
tries.  
5

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
DFN8 5×6.15, 1.27
P
,
D
UAL COOL  
CASE 506EG  
ISSUE D  
DATE 25 AUG 2020  
GENERIC  
MARKING DIAGRAM*  
AYWWZZ  
XXXXXX  
XXXX = Specific Device Code  
*This information is generic. Please refer to  
A
Y
= Assembly Location  
=
Y
e
ar  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
WW =
 
Work Week  
ZZ  
= Assembly Lot Code  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON84257G  
DFN8 5×6.15, 1.27
P
,
D
UAL COOL  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2018  

onsemi
,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates  
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.
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−
is” and
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onsemi
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onsemi
. “Typical” parameters which may be provided in
onsemi
data sheets and/or specifications can and do vary in different applications and actual performance may  
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