onsemi-NTMS5P02R2
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Download  | onsemi-NTMS5P02R2 |
NTMS5P02, NVMS5P02
P-Channel, Enhancement
Mode, SOIC-8
-5.4 A, -20 V
Features
V
R
TYP
I MAX
D
•
High Density Power MOSFET with Ultra Low R
DSS
DS(ON)
DS(on)
Providing Higher Efficiency
−
20 V
26 m
W
@
−
4.5 V
−
5.4 A
•
Miniature SOIC
−
8 Surface Mount Package
−
Saves Board Space
•
Diode Exhibits High Speed with Soft Recovery
•
I
Specified at Elevated Temperature
•
Drain
−
to
−
Source Avalanche Energy Specified
DSS
Single P
−
Channel
D
•
Mounting Information for the SOIC
−
8 Package is Provided
•
These Devices are Pb
−
Free and are RoHS Compliant
•
NVMS Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC
−
Q101
Qualified and PPAP Capable
G
S
Applications
MARKING DIAGRAM &
PIN ASSIGNMENT
•
Power Management in Portable and Battery
−
Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
D
D
D
D
8
8
1
E5P02x
AYWW
G
G
SOIC
−
8
CASE 751
STYLE 13
1
NC S
S
G
E5P02 =
Specific Device Code
x
= Blank or S
A
Y
= Assembly Location
=
Y
e
ar
WW
G
= Work Week
= Pb
−
Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
Package
Shipping
NTMS5P02R2G
SOIC
−
8 2500
/
T
a
pe & Reel
(Pb
−
Free)
NVMS5P02R2G
SOIC
−
8 2500
/
T
a
pe & Reel
(Pb
−
Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
June, 2019
−
Rev. 3
NTMS5P02R2/D
NTMS5P02, NVMS5P02
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol
Value
−
20
−
20
10
Unit
V
Drain
−
to
−
Source Voltage
V
DSS
DGR
Drain
−
to
−
Gate Voltage (R
= 1.0 m
W
)
V
V
GS
Gate
−
to
−
Source Voltage
−
Continuous
V
GS
V
Thermal Resistance
−
Junction
−
to
−
Ambient (Note 1)
R
50
2.5
−
7.05
−
5.62
1.2
−
4.85
−
28
°
C/W
W
A
q
P
D
D
D
D
D
JA
T
o
tal Power Dissipation @ T
= 25
°
C
A
Continuous Drain Current @ 25
°
C
Continuous Drain Current @ 70
°
C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
I
I
P
A
W
A
A
I
I
DM
Thermal Resistance
−
R
85
°
C/W
W
A
q
JA
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
1.47
−
5.40
−
4.30
0.7
A
Continuous Drain Current @ 25
°
C
Continuous Drain Current @ 70
°
C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
I
I
P
D
D
D
D
A
W
A
A
I
−
3.72
−
20
I
DM
Thermal Resistance
−
R
159
0.79
−
3.95
−
3.15
0.38
−
2.75
−
12
°
C/W
W
A
q
JA
T
o
tal Power Dissipation @ T
= 25
°
C
P
D
A
Continuous Drain Current @ 25
°
C
Continuous Drain Current @ 70
°
C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
I
I
P
D
D
D
D
A
W
A
A
I
I
DM
Operating and Storage
T
e
mperature Range
Single Pulse Drain
−
to
−
Source Avalanche Energy
−
Starting T
= 25
°
C
T , T
−
55 to +150
°
C
J
stg
E
AS
360
mJ
J
(V =
−
20 Vdc, V
=
−
5.0 Vdc, Peak I
=
−
8.5 Apk, L = 10 mH, R
= 25
W
)
DD
GS
L
G
Maximum Lead
T
e
mperature for Soldering Purposes, 1/8
″
from case for 10 seconds
T
L
260
°
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Mounted
onto a 2
″
square FR
−
4 Board (1
″
sq. 2 oz Cu 0.06
″
thick single sided), t
≤
10 seconds.
2. Mounted
onto a 2
″
square FR
−
4 Board (1
″
sq. 2 oz Cu 0.06
″
thick single sided), t = steady state.
3. Minimum
FR
−
4 or G
−
10 PCB, t = Steady State.
4. Pulse
T
e
st: Pulse Width = 300
m
s, Duty Cycle = 2%.
2
NTMS5P02, NVMS5P02
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
(V =
0 Vdc, I
=
−
250
m
Adc)
V
Vdc
(BR)DSS
−
20
−
−
−
15
−
−
GS
D
T
e
mperature Coefficient (Positive)
mV/
°
C
m
Adc
Zero Gate Voltage Drain Current
I
DSS
(V =
−
16 Vdc, V
= 0 Vdc, T
= 25
°
C)
−
−
−
−
−
−
0.2
−
1.0
−
10
−
DS
GS
J
(V =
−
16 Vdc, V
= 0 Vdc, T
= 125
°
C)
DS
GS
J
(V =
−
20 Vdc, V
= 0 Vdc, T
= 25
°
C)
DS
GS
J
Gate
−
Body Leakage Current
(V =
−
10 Vdc, V
= 0 Vdc)
I
I
nAdc
nAdc
GSS
−
−
−
−
−
100
GS
DS
Gate
−
Body Leakage Current
(V =
+10 Vdc, V
= 0 Vdc)
GSS
100
GS
DS
ON CHARACTERISTICS
Gate Threshold Voltage
V
GS(th)
Vdc
(V =
V ,
I =
−
250
m
Adc)
−
0.65
−
0.9
−
1.25
DS
GS
D
T
e
mperature Coefficient (Negative)
−
2.9
−
mV/
°
C
Static Drain
−
to
−
Source On
−
State Resistance
R
W
DS(on)
(V =
−
4.5 Vdc, I
=
−
5.4 Adc)
−
−
0.026
0.037
0.033
0.048
GS
D
(V =
−
2.5 Vdc, I
=
−
2.7 Adc)
GS
D
Forward Transconductance (V
=
−
9.0 Vdc, I
=
−
5.4 Adc)
g
FS
−
15
−
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
1375
510
1900
900
iss
(V =
−
16 Vdc, V
= 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
200
380
rss
Turn
−
On Delay Time
t
−
−
−
−
−
−
−
−
−
−
−
18
25
70
55
22
70
65
90
20
4.0
7.0
35
50
125
100
−
ns
ns
d(on)
(V =
−
16 Vdc, I
=
−
1.0 Adc,
DD
D
Rise Time
t
r
V
=
−
4.5 Vdc,
= 6.0
W
)
GS
Turn
−
Off Delay Time
Fall Time
t
t
t
d(off)
R
G
t
f
Turn
−
On Delay Time
Rise Time
d(on)
(V =
−
16 Vdc, I
=
−
5.4 Adc,
DD
D
t
r
−
V
GS
=
−
4.5 Vdc,
= 6.0
W
)
Turn
−
Off Delay Time
Fall Time
−
d(off)
R
G
t
f
−
T
o
tal Gate Charge
Gate
−
Source Charge
Gate
−
Drain Charge
Q
35
−
nC
tot
gs
gd
(V =
−
16 Vdc,
DS
Q
Q
V
GS
=
−
4.5 Vdc,
=
−
5.4 Adc)
I
D
−
Diode Forward On
−
Voltage
(I =
−
5.4 Adc, V
= 0 V)
V
−
−
−
0.95
−
0.72
−
1.25
−
Vdc
ns
S
GS
SD
(I =
−
5.4 Adc, V
= 0 Vdc, T
= 125
°
C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
40
20
75
−
rr
(I =
−
5.4 Adc, V
= 0 Vdc,
S
GS
t
a
dI /dt
= 100 A/
m
s)
S
t
20
−
b
Reverse Recovery Stored Charge
Q
0.03
−
m
C
RR
5. Handling
precautions to protect against electrostatic discharge is mandatory.
6. Indicates
Pulse
T
e
st: Pulse Width = 300
m
s max, Duty Cycle = 2%.
7. Switching
characteristics are independent of operating junction temperature.
3
NTMS5P02, NVMS5P02
12
12
10
−
8 V
−
2.3 V
−
4.5 V
−
3.7 V
−
3.1 V
V
DS
≥
−
10 V
T =
25
°
C
J
10
8
−
2.1 V
8
6
4
−
2.7 V
−
2.5 V
6
−
1.9 V
−
1.7 V
100
°
C
4
25
°
C
T =
−
55
°
C
J
2
0
2
0
V
=
−
1.3 V
GS
0
0.25
0.5
0.75
1
1.25
1.5 1.75
2
1
1.5
2
2.5
3
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
0.08
0.06
0.04
0.05
0.04
0.03
I
=
−
5.4 A
D
T =
25
°
C
J
T =
25
°
C
J
V
V
=
−
2.5 V
=
−
2.7 V
GS
GS
V
GS
=
−
4.5 V
0.02
0
0.02
0.01
0
2
4
6
8
10
2
4
6
8
10
12
−
V ,
GATE
−
TO
−
SOURCE VOLTAGE (VOLTS)
GS
−
I ,
DRAIN CURRENT (AMPS)
D
Figure 3. On
−
Resistance versus
Gate
−
To
−
Source Voltage
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
1.6
1.4
1.2
1
10,000
1000
100
V
= 0 V
GS
I
V
=
−
5.4 A
D
T =
150
°
C
=
−
4.5 V
J
GS
T =
125
°
C
J
0.8
0.6
−
50
−
25
0
25
50
75
100
125
150
2
4
6
8
10
12
14
16
18 20
T , JUNCTION TEMPERATURE (
°
C)
J
−
V ,
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
To
−
Source Leakage Current
Temperature
versus Voltage
4
NTMS5P02, NVMS5P02
5
20
16
12
8
V
DS
= 0 V
V
GS
= 0 V
QT
4000
3000
2000
C
C
T =
25
°
C
J
iss
−
V
GS
4
3
2
−
V
DS
Q1
Q2
rss
C
iss
I
=
−
5.4 A
D
1000
0
T =
25
°
C
J
1
0
4
0
C
oss
C
0
rss
0
4
8
12
16
20
24
10
5
5
10
15
20
−
V
GS
−
V
DS
Q ,
TOTAL GATE CHARGE (nC)
g
Figure 8. Gate
−
To
−
Source and Drain
−
To
−
Source
GATE
−
TO
−
SOURCE OR
Voltage versus Total Charge
DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
V
=
−
16 V
=
−
5.4 A
=
−
4.5 V
DD
5
4
3
2
V
= 0 V
GS
I
D
T =
25
°
C
J
V
GS
t
t
d(off)
f
t
r
100
10
t
d(on)
1
0
1
10
R ,
GATE RESISTANCE (OHMS)
100
0.2 0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
−
V ,
SOURCE
−
TO
−
DRAIN VOLTAGE (VOLTS)
SD
G
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
DRAIN
−
TO
−
SOURCE DIODE CHARACTERISTICS
100
10
V
= 20 V
GS
SINGLE PULSE
1 ms
T
C
= 25
°
C
di/dt
I
S
10 ms
t
rr
1
t
a
t
b
R
LIMIT
DS(on)
TIME
THERMAL LIMIT
PACKAGE LIMIT
0.25 I
t
p
dc
S
0.1
0.1
1
10
100
I
S
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Diode Reverse Recovery Waveform
5
NTMS5P02, NVMS5P02
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.05
0.1
Normalized to
q
ja at 10s.
0.02
0.01
Chip
0.0163
W
0.0652
W
0.1988
W
0.6411
W
0.9502
W
0.01
0.0307 F
0.1668 F
0.5541 F
1.9437 F
72.416 F
Ambient
1.0E+03
SINGLE PULSE
0.001
1.0E
−
05 1.0E
−
04
1.0E
−
03
1.0E
−
02
1.0E
−
01
t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
Figure 13. Thermal Response
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING
AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETER.
3. DIMENSION
A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−
X
−
A
4. MAXIMUM
MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION
D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751
−
01 THRU 751
−
06 ARE OBSOLETE. NEW
STANDARD IS 751
−
07.
S
M
M
Y
B
0.25 (0.010)
1
K
−
Y
−
MILLIMETERS
DIM MIN
MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N
X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−
Z
−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb
−
Free)
IC
IC
(Pb
−
Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
=
Y
e
ar
Y
Y
W
G
=
Y
e
ar
= Work Week
= Pb
−
Free Package
WW
G
= Work Week
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC
−
8 NB
PAGE 1 OF 2
onsemi
and
are trademarks of Semiconductor Components Industries, LLC dba
onsemi
or its subsidiaries in the United States and/or other countries.
onsemi
reserves
the right to make changes without further notice to any products herein.
onsemi
makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does
onsemi
assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages.
onsemi
does not convey any license under its patent rights nor the rights of others.
©
Semiconductor Components Industries, LLC, 2019
SOIC
−
8 NB
CASE 751
−
07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1.
EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1.
COLLECTOR, DIE, #1
2. COLLECTOR,
#1
3. COLLECTOR,
#2
4. COLLECTOR,
#2
5. BASE,
#2
PIN 1.
DRAIN, DIE #1
2. DRAIN,
#1
3. DRAIN,
#2
4. DRAIN,
#2
5. GATE,
#2
PIN 1.
ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER,
#2
7. BASE,
#1
6. SOURCE,
#2
7. GATE,
#1
7. BASE
8. EMITTER
8. EMITTER,
#1
8. SOURCE,
#1
8. COMMON
CATHODE
STYLE 5:
STYLE 6:
PIN 1.
SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1.
COLLECTOR, DIE #1
2. BASE,
#1
PIN 1.
DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1.
INPUT
2. EXTERNAL
BYPASS
3. THIRD
STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE
3
7. SECOND
STAGE Vd
8. FIRST
STAGE Vd
3. DRAIN
3. BASE,
#2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR,
#2
5. COLLECTOR,
#2
6. EMITTER,
#2
7. EMITTER,
#1
8. COLLECTOR,
#1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1.
GROUND
2. BIAS
1
STYLE 11:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 12:
PIN 1.
EMITTER, COMMON
2. COLLECTOR,
DIE #1
3. COLLECTOR,
DIE #2
4. EMITTER,
COMMON
5. EMITTER,
COMMON
6. BASE,
DIE #2
PIN 1.
SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS
2
7. INPUT
8. GROUND
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. DRAIN
2
7. DRAIN
1
8. DRAIN
1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE,
DIE #1
8. EMITTER,
COMMON
STYLE 13:
PIN 1.
N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1.
N
−
SOURCE
2. N
−
GATE
STYLE 15:
PIN 1.
ANODE 1
2. ANODE
1
STYLE 16:
PIN 1.
EMITTER, DIE #1
2. BASE,
DIE #1
3. P
−
SOURCE
4. P
−
GATE
5. P
−
DRAIN
6. P
−
DRAIN
7. N
−
DRAIN
8. N
−
DRAIN
3. ANODE
1
4. ANODE
1
5. CATHODE,
COMMON
6. CATHODE,
COMMON
7. CATHODE,
COMMON
8. CATHODE,
COMMON
3. EMITTER,
DIE #2
4. BASE,
DIE #2
5. COLLECTOR,
DIE #2
6. COLLECTOR,
DIE #2
7. COLLECTOR,
DIE #1
8. COLLECTOR,
DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1.
VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 20:
PIN 1.
ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1.
SOURCE (N)
2. GATE
(N)
3. SOURCE
(P)
4. GATE
(P)
5. DRAIN
3. SOURCE
2
4. GATE
2
5. DRAIN
2
6. MIRROR
2
7. DRAIN
1
8. MIRROR
1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1.
CATHODE 1
2. CATHODE
2
3. CATHODE
3
4. CATHODE
4
5. CATHODE
5
6. COMMON
ANODE
7. COMMON
ANODE
8. CATHODE
6
PIN 1.
I/O LINE 1
PIN 1.
LINE 1 IN
PIN 1.
BASE
2. COMMON
CATHODE/VCC
3. COMMON
CATHODE/VCC
4. I/O
LINE 3
5. COMMON
ANODE/GND
6. I/O
LINE 4
7. I/O
LINE 5
8. COMMON
ANODE/GND
2. COMMON
ANODE/GND
3. COMMON
ANODE/GND
4. LINE
2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE
2 OUT
6. COMMON
ANODE/GND
7. COMMON
ANODE/GND
8. LINE
1 OUT
STYLE 25:
PIN 1.
VIN
2. N/C
STYLE 26:
PIN 1.
GND
2. dv/dt
STYLE 27:
PIN 1.
ILIMIT
2. OVLO
STYLE 28:
PIN 1.
SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1.
DRAIN 1
2. DRAIN
1
STYLE 29:
PIN 1.
BASE, DIE #1
2. EMITTER,
#1
3. BASE,
#2
3. GATE
2
4. SOURCE
2
5. SOURCE
1/DRAIN 2
6. SOURCE
1/DRAIN 2
7. SOURCE
1/DRAIN 2
8. GATE
1
4. EMITTER,
#2
5. COLLECTOR,
#2
6. COLLECTOR,
#2
7. COLLECTOR,
#1
8. COLLECTOR,
#1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
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DOCUMENT NUMBER:
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8 NB
PAGE 2 OF 2
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