onsemi-NTMTS0D7N06CTXG
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N-Channel, DFNW8
60
V
,
0
.72 m
W
, 464 A
NTMTS0D7N06C
Features
•
Small Footprint (8×8 mm) for Compact Design
•
Low R
to Minimize Conduction Losses
DS(on)
•
Low Q
and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
•
These Devices are Pb
−
Free, Halogen Free/BFR Free and are RoHS
Compliant
60 V
0.72 m
W
@ 10 V
464 A
Typical Applications
•
Power Tools, Battery Operated
V
a
cuums
•
U
A
V
/Drones, Material Handling
•
BMS/Storage, Home Automation
D (5
−
8)
G (1)
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Parameter
Drain
−
to
−
Source Voltage
Symbol
Value
60
Unit
V
S (2
−
4)
V
DSS
N
−
CHANNEL MOSFET
Gate
−
to
−
Source Voltage
V
GS
20
V
Continuous Drain
Steady
State
T
= 25
°
C
= 100
°
C
= 25
°
C
I
464
A
C
D
Current R
q
JC
T
C
328.1
294.6
147.3
60.5
42.7
5.0
Power Dissipation
T
C
P
W
A
D
R
q
JC
T
C
= 100
°
C
Continuous Drain
Current R
Steady
State
T =
25
°
C
A
I
D
q
JA
T =
100
°
C
A
Power Dissipation
T =
25
°
C
A
P
W
DFNW8
CASE 507AP
D
R
q
JA
T =
100
°
C
A
2.5
Pulsed Drain Current
T =
25
°
C, t
= 10
m
s
I
DM
900
A
A
p
MARKING DIAGRAM
Operating Junction and Storage
T
e
mperature
Range
T , T
−
55 to
+175
°
C
J
stg
Source Current (Body Diode)
I
245.5
1754
A
S
0D7N06C
AWLYWW
Single Pulse Drain
−
to
−
Source Avalanche
E
AS
mJ
Energy (I
= 40 A)
L(pk)
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
L
260
°
C
A
= Assembly Location
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
WL =
2
−
digit Wafer Lot Code
=
Y
ear Code
WW = Work Week Code
Y
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
0.5
Unit
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
R
°
C/W
q
JC
R
30
q
JA
2
1. Surface
−
mounted on FR4 board using a 1 in
pad size, 1 oz. Cu pad.
2. The
entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
©
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
December, 2020
−
Rev. 3
NTMTS0D7N06C/D
NTMTS0D7N06C
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain
−
to
−
Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
60
V
(BR)DSS
D
Drain
−
to
−
Source Breakdown Voltage
T
e
mperature Coefficient
V
/
I
D
= 250
m
A, ref to 25
°
C
24.7
(BR)DSS
mV/
°
C
T
J
Zero Gate Voltage Drain Current
I
V
= 0
V
,
T =
25
°
C
10
DSS
GS
DS
J
V
= 60 V
m
A
T =
125
°
C
J
250
100
Gate
−
to
−
Source Leakage Current
Gate Threshold Voltage
I
V
= 0
V
, V
=
2
0 V
nA
GSS
DS
GS
GS
V
V
= V
, I
= 250
m
A
2.0
4.0
V
mV/
°
C
m
W
S
GS(TH)
DS
D
Negative Threshold
T
e
mperature Coefficient
Drain
−
to
−
Source On Resistance
Forward Transconductance
V
/T
J
I
= 250
m
A, ref to 25
°
C
−
7.93
0.55
250
GS(TH)
D
R
V
GS
= 10 V
I =
50 A
D
0.72
DS(on)
g
FS
V =5
V
, I
=
5
0 A
DS D
Gate Resistance
R
T =
25
°
C
A
1.0
W
G
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
C
11535
8010
174
ISS
Output Capacitance
C
V
V
= 0
V
, f = 1
M
Hz, V
= 30 V
pF
nC
OSS
RSS
GS
DS
Reverse Transfer Capacitance
Threshold Gate Charge
Gate
−
to
−
Source Charge
Gate
−
to
−
Drain Charge
T
o
tal Gate Charge
C
Q
25.7
40.0
20.7
152
G(TH)
Q
GS
Q
= 10
V
, V
=
3
0 V; I
= 50 A
GD
GS
DS
D
Q
Q
G(TOT)
Voltage Plateau
V
3.71
72
V
GP
T
o
tal Gate Charge
V
GS
= 4.5
V
, V
=
3
0 V; I
= 50 A
nC
G(TOT)
DS
D
Turn
−
On Delay Time
t
39.7
29.3
127
d(ON)
Rise Time
t
r
V
= 10
V
, V
=
3
0
V
,
DS
GS
D
ns
V
I
= 50 A, R
= 6
W
G
Turn
−
Off Delay Time
t
d(OFF)
Fall Time
t
42.6
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
0.72
0.59
120
60
1.2
SD
RR
J
V
S
= 0
V
,
GS
I
= 50 A
T =
125
°
C
J
Reverse Recovery Time
Charge Time
t
t
a
ns
V
= 0
V
,
d
IS/dt = 100 A/
m
s,
GS
I
S
= 50 A
Discharge Time
t
b
60
Reverse Recovery Charge
Q
324
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse
T
e
st: pulse width
v
300
m
s, duty cycle
v
2%.
4. Switching
characteristics are independent of operating junction temperatures.
2
NTMTS0D7N06C
TYPICAL CHARACTERISTICS
1000
900
800
700
600
500
400
300
200
100
0
800
10 V
6.0 V
V
DS
= 10 V
700
600
500
400
300
V
GS
= 5.0 V
4.5 V
T =
25
°
C
J
200
100
0
T =
125
°
C
J
3.6 V
T =
−
55
°
C
J
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. Transfer Characteristics
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
0.8
0.7
0.6
T =
25
°
C
D
J
T =
25
°
C
D
J
I
= 50 A
I
= 50 A
V
GS
= 10 V
0.2
0
0.5
0.4
4
5
6
7
8
9
10
10 90
170 250 330 410 490 570 650 730
810
V
GS
, GATE
−
TO
−
SOURCE VOLTAGE (V)
I ,
DRAIN CURRENT (A)
D
Figure 3. On
−
Resistance vs. Gate
−
to
−
Source
Figure 4. On
−
Resistance vs. Drain Current and
Voltage
Gate Voltage
2.00
1.75
1.50
1.25
1.00
1E+00
1E
−
01
1E
−
02
1E
−
03
1E
−
04
1E
−
05
1E
−
06
1E
−
07
V
= 10 V
= 50 A
GS
I
D
T =
175
°
C
T =
150
°
C
J
J
T =
125
°
C
J
T =
85
°
C
J
1E
−
08
1E
−
09
1E
−
10
T =
25
°
C
J
0.75
0.50
0
25
50
75
100
125
150
175
5
15
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
DS
25
35
45
55
T , JUNCTION TEMPERATURE (
°
C)
V
J
Figure 5. On
−
Resistance Variation with
Figure 6. Drain
−
to
−
Source Leakage Current
Temperature
vs. Voltage
3
NTMTS0D7N06C
TYPICAL CHARACTERISTICS
10
9
100K
10K
C
ISS
8
7
6
5
C
OSS
1K
Q
Q
GD
GS
4
3
2
1
0
100
10
C
V =
30 V
DS
RSS
V
= 0 V
GS
T =
25
°
C
T =
25
°
C
J
J
I
D
= 50 A
f = 1 MHz
0
20
40
60
80
100
120
140
0.01
0.1
1
10
100
Q ,
TOTAL GATE CHARGE (nC)
G
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate
−
to
−
Source Voltage vs. Total
Charge
1000
50
40
30
20
V
GS
= 0 V
t
t
d(off)
t
f
T =
175
°
C
J
t
r
T =
150
°
C
J
d(on)
100
10
T =
125
°
C
J
T =
25
°
C
J
V
= 10 V
= 30 V
10
0
GS
V
DS
I
T =
−
55
°
C
J
= 50 A
D
2
6
10 14 18 22 26 30 34 38 42 46 50
R ,
GATE RESISTANCE (
W
)
0
0.1 0.2
0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
, SOURCE
−
TO
−
DRAIN VOLTAGE (V)
V
SD
G
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
1000
100
10
T
= 25
°
C
J(initial)
10
m
s
0.5 ms
1 ms
10 ms
T
= 25
°
C
C
Single Pulse
≤
10 V
10
1
T
= 100
°
C
J(initial)
V
GS
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0.1
1
10
100
0.00001
0.0001
0.001
0.01
V
DS
, DRAIN
−
TO
−
SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
4
NTMTS0D7N06C
TYPICAL CHARACTERISTICS
100
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
Single Pulse
0.001
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
†
Marking
Package
DFNW8
Shipping
NTMTS0D7N06CTXG
0D7N06C
3000 /
T
a
pe & Reel
(Pb
−
Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFNW8 8.3×8.4, 2P
CASE 507AP
ISSUE C
DATE 11 JUN 2020
GENERIC
MARKING DIAGRAM*
XXXXXXXX
AWLYWW
XXXX = Specific Device Code
A
= Assembly Location
WL =
Wafer Lot Code
=
Y
ear Code
Y
WW =
Work Week Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON80534G
DFNW8 8.3×8.4, 2P
PAGE 1 OF 1
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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©
Semiconductor Components Industries, LLC, 2018
ON Semiconductor and
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−
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